System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints

TL;DR

This work tackles the challenge of optimizing end-to-end EtoE latency in multi-component embedded systems by introducing EtoE-DSE, a holistic system-level design-space exploration framework. The method combines an EtoE latency estimation model, EPF pathfinding, FDSS space segmentation, and an elite GA-based LCSO to efficiently identify Pareto-optimal configurations that balance energy and area while satisfying EtoE latency constraints. Across a real-world autonomous driving subsystem implemented on FPGA, EtoE-DSE achieves up to 89.26% QoR improvement over prior DSE approaches and dramatically reduces the design space by orders of magnitude. The approach enables scalable, timing-aware hardware design for complex, multi-component systems with variable timing requirements, with potential for further gains from advanced latency modeling and learning-based predictive techniques.

Abstract

Many modern embedded systems have end-to-end (EtoE) latency constraints that necessitate precise timing to ensure high reliability and functional correctness. The combination of High-Level Synthesis (HLS) and Design Space Exploration (DSE) enables the rapid generation of embedded systems using various constraints/directives to find Pareto-optimal configurations. Current HLS DSE approaches often address latency by focusing on individual components, without considering the EtoE latency during the system-level optimization process. However, to truly optimize the system under EtoE latency, we need a holistic approach that analyzes individual system components' timing constraints in the context of how the different components interact and impact the overall design. This paper presents a novel system-level HLS DSE approach, called EtoE-DSE, that accommodates EtoE latency and variable timing constraints for complex multi-component application-specific embedded systems. EtoE-DSE employs a latency estimation model and a pathfinding algorithm to identify and estimate the EtoE latency for paths between any endpoints. It also uses a frequency-based segmentation process to segment and prune the design space, alongside a latency-constrained optimization algorithm for efficiently and accurately exploring the system-level design space. We evaluate our approach using a real-world use case of an autonomous driving subsystem compared to the state-of-the-art in HLS DSE. We show that our approach yields substantially better optimization results than prior DSE approaches, improving the quality of results by up to 89.26%, while efficiently identifying Pareto-optimal configurations in terms of energy and area.

Figures (11)

• Figure 1: The proposed End-to-End Design Space Exploration (EtoE-DSE) methodology to find system-level Pareto-optimal configurations while meeting the variable timing and end-to-end (EtoE) latency constraints.
• Figure 2: An example of a Periodic State Machine (PSM) model using a behavior planning component in the autonomous driving subsystem.
• Figure 3: A block diagram for the behavior planning PSM in an autonomous driving subsystem to illustrate the relationship between PSM, FSM, MCC, and both HandshakeIn and HandshakeOut components.
• Figure 4: A simplified illustration of an event handshaking protocol between sender PSM and receiver PSM.
• Figure 5: An example of end-to-end (EtoE) latency and variable timing constrained system-level state-based graph.