Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Are LLMs Any Good for High-Level Synthesis?

Yuchao Liao, Tosiron Adegbija, Roman Lysecky

TL;DR

The paper assesses whether Large Language Models can meaningfully augment High-Level Synthesis by translating natural language and C specifications into Verilog and comparing against conventional HLS tooling. It introduces a taxonomy of LLM roles in HLS, surveys the state-of-the-art, and conducts an empirical evaluation on nine PolyBench kernels using four design flows. Results show LLM-based approaches often achieve substantial reductions in resource usage, execution cycles, and power for most benchmarks, though the critical-path delay remains a concern and energy costs of LLMs raise sustainability questions. The work highlights the importance of HITL, prompting strategies, and careful integration of LLMs into hardware design workflows to realize practical benefits in AI accelerators, embedded systems, and HPC contexts.

Abstract

The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.

Are LLMs Any Good for High-Level Synthesis?

TL;DR

The paper assesses whether Large Language Models can meaningfully augment High-Level Synthesis by translating natural language and C specifications into Verilog and comparing against conventional HLS tooling. It introduces a taxonomy of LLM roles in HLS, surveys the state-of-the-art, and conducts an empirical evaluation on nine PolyBench kernels using four design flows. Results show LLM-based approaches often achieve substantial reductions in resource usage, execution cycles, and power for most benchmarks, though the critical-path delay remains a concern and energy costs of LLMs raise sustainability questions. The work highlights the importance of HITL, prompting strategies, and careful integration of LLMs into hardware design workflows to realize practical benefits in AI accelerators, embedded systems, and HPC contexts.

Abstract

The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.
Paper Structure (21 sections, 7 figures, 2 tables)

This paper contains 21 sections, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Taxonomy of LLM for HLS
  3. LLM as Specification Generator
  4. LLM as Code Generator
  5. LLM as Hardware Verification Assistant
  6. LLM as Design Space Exploration Assistant
  7. Survey of the State-of-the-Art in LLMs for HLS
  8. LLMs Used for HLS
  9. Applications
  10. Input and Output Modalities
  11. Benchmarking and Evaluation
  12. Experimental Methodology
  13. HLS Approach
  14. LLM-Assisted HLS Approaches
  15. C$\rightarrow$LLM$\rightarrow$Verilog
  16. ...and 6 more sections

Figures (7)

  • Figure 1: Taxonomy of LLM applications in HLS
  • Figure 2: HLS-based (a) and LLM-based (b) approaches to generating hardware accelerators
  • Figure 3: Background, role, and constraints
  • Figure 4: Inputs and error checking (I/O)
  • Figure 5: Inputs and error checking (loop)
  • ...and 2 more figures