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Tywaves: A Typed Waveform Viewer for Chisel

Raffaele Meloni, H. Peter Hofstee, Zaid Al-Ars

TL;DR

Tywaves tackles the challenge of debugging modern, type-rich HDL code by embedding a type-centered waveform viewer into the Chisel-CIRCT toolchain, preserving source-level data types and hierarchical structures in waveforms. It achieves this through a new AddTywavesAnnotation phase in Chisel elaboration, an extended CIRCT debug dialect (including dbg.enumdef, dbg.subfield, and dbg.moduleinfo), and integration with Surfer via tywaves-rs, enabling a richer, type-aware UI and data flow. A ChiselSim-based API enables easy adoption, demonstrated on the ChiselWatt OpenPOWER-inspired processor to show clearer opcodes, states, and signal aggregates. The work provides a practical, open-source path to extend type-aware debugging across HDLs by leveraging CIRCT/MLIR and open waveform viewers, improving debugging productivity and code comprehension.

Abstract

Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted HDL that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. However, while these language features significantly improve the process of writing code, debugging Chisel designs with open source tools loses many of the advantages of the source language, as type information and data structure hierarchies are lost in the translation, simulator output, and waveform viewer. This work, Tywaves, presents a new type-centered debugging format that brings the same level of abstraction found in contemporary hardware languages to waveform viewers. Contributions to the Chisel library and CIRCT MLIR compiler as well as the Surfer waveform viewer result in a waveform viewer that better supports the Chisel HDL. Project url: https://github.com/rameloni/tywaves-chisel-demo

Tywaves: A Typed Waveform Viewer for Chisel

TL;DR

Tywaves tackles the challenge of debugging modern, type-rich HDL code by embedding a type-centered waveform viewer into the Chisel-CIRCT toolchain, preserving source-level data types and hierarchical structures in waveforms. It achieves this through a new AddTywavesAnnotation phase in Chisel elaboration, an extended CIRCT debug dialect (including dbg.enumdef, dbg.subfield, and dbg.moduleinfo), and integration with Surfer via tywaves-rs, enabling a richer, type-aware UI and data flow. A ChiselSim-based API enables easy adoption, demonstrated on the ChiselWatt OpenPOWER-inspired processor to show clearer opcodes, states, and signal aggregates. The work provides a practical, open-source path to extend type-aware debugging across HDLs by leveraging CIRCT/MLIR and open waveform viewers, improving debugging productivity and code comprehension.

Abstract

Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted HDL that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. However, while these language features significantly improve the process of writing code, debugging Chisel designs with open source tools loses many of the advantages of the source language, as type information and data structure hierarchies are lost in the translation, simulator output, and waveform viewer. This work, Tywaves, presents a new type-centered debugging format that brings the same level of abstraction found in contemporary hardware languages to waveform viewers. Contributions to the Chisel library and CIRCT MLIR compiler as well as the Surfer waveform viewer result in a waveform viewer that better supports the Chisel HDL. Project url: https://github.com/rameloni/tywaves-chisel-demo
Paper Structure (19 sections, 3 figures, 2 tables)

This paper contains 19 sections, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Chisel
  4. Chisel compilation and CIRCT
  5. Chisel simulation
  6. CIRCT debug dialect
  7. Typed hardware
  8. Related work
  9. Implementation
  10. Updates in Chisel
  11. Updated CIRCT debug dialect
  12. New dbg.enumdef
  13. Updated dbg.variable
  14. New dbg.subfield
  15. New dbg.moduleinfo
  16. ...and 4 more sections

Figures (3)

  • Figure 1: Chisel compilation and simulation flow
  • Figure 2: Tywaves integration within the Surfer waveform viewer
  • Figure 3: Comparison between Tywaves and standard waveform outputs for simulation of ChiselWatt. Opcode represented as enums; State of computational units; Aggregated signal hierarchies; Types enable clearer distinctions; Chisel bindings and Chisel-Scala types.