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In-Memory Learning Automata Architecture using Y-Flash Cell

Omar Ghazal, Tian Lan, Shalman Ojukwu, Komal Krishnamurthy, Alex Yakovlev, Rishad Shafik

TL;DR

The paper tackles the data-movement bottleneck in machine learning by leveraging in-memory computing with Y-Flash floating-gate memristors to implement Tsetlin Machine learning automata directly in memory. It introduces a mapping where TA states are encoded as analog conductances of a single Y-Flash cell, enabled by its dual-transistor structure and CMOS compatibility, and it validates this approach with device-level characterization and a compact TA-to-conductance mapping. The results show 40 discrete TA states per device (extendable to ~1000) and robust D2D/C2C performance across 100 devices and 250 cycles, with quantifiable read/write energies and times. A XOR-based training demonstration illustrates that TA dynamics can be efficiently realized with a reduced write-pulse budget, indicating scalable, edge-friendly in-memory learning. This work suggests a viable path toward energy-efficient, scalable on-edge TM implementations using standard-CMOS compatible memristors.

Abstract

The modern implementation of machine learning architectures faces significant challenges due to frequent data transfer between memory and processing units. In-memory computing, primarily through memristor-based analog computing, offers a promising solution to overcome this von Neumann bottleneck. In this technology, data processing and storage are located inside the memory. Here, we introduce a novel approach that utilizes floating-gate Y-Flash memristive devices manufactured with a standard 180 nm CMOS process. These devices offer attractive features, including analog tunability and moderate device-to-device variation; such characteristics are essential for reliable decision-making in ML applications. This paper uses a new machine learning algorithm, the Tsetlin Machine (TM), for in-memory processing architecture. The TM's learning element, Automaton, is mapped into a single Y-Flash cell, where the Automaton's range is transferred into the Y-Flash's conductance scope. Through comprehensive simulations, the proposed hardware implementation of the learning automata, particularly for Tsetlin machines, has demonstrated enhanced scalability and on-edge learning capabilities.

In-Memory Learning Automata Architecture using Y-Flash Cell

TL;DR

The paper tackles the data-movement bottleneck in machine learning by leveraging in-memory computing with Y-Flash floating-gate memristors to implement Tsetlin Machine learning automata directly in memory. It introduces a mapping where TA states are encoded as analog conductances of a single Y-Flash cell, enabled by its dual-transistor structure and CMOS compatibility, and it validates this approach with device-level characterization and a compact TA-to-conductance mapping. The results show 40 discrete TA states per device (extendable to ~1000) and robust D2D/C2C performance across 100 devices and 250 cycles, with quantifiable read/write energies and times. A XOR-based training demonstration illustrates that TA dynamics can be efficiently realized with a reduced write-pulse budget, indicating scalable, edge-friendly in-memory learning. This work suggests a viable path toward energy-efficient, scalable on-edge TM implementations using standard-CMOS compatible memristors.

Abstract

The modern implementation of machine learning architectures faces significant challenges due to frequent data transfer between memory and processing units. In-memory computing, primarily through memristor-based analog computing, offers a promising solution to overcome this von Neumann bottleneck. In this technology, data processing and storage are located inside the memory. Here, we introduce a novel approach that utilizes floating-gate Y-Flash memristive devices manufactured with a standard 180 nm CMOS process. These devices offer attractive features, including analog tunability and moderate device-to-device variation; such characteristics are essential for reliable decision-making in ML applications. This paper uses a new machine learning algorithm, the Tsetlin Machine (TM), for in-memory processing architecture. The TM's learning element, Automaton, is mapped into a single Y-Flash cell, where the Automaton's range is transferred into the Y-Flash's conductance scope. Through comprehensive simulations, the proposed hardware implementation of the learning automata, particularly for Tsetlin machines, has demonstrated enhanced scalability and on-edge learning capabilities.
Paper Structure (6 sections, 7 figures, 2 tables)

This paper contains 6 sections, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Y-Flash Based Tsetlin Automaton Implementation
  3. Y-Flash Cell characteristics
  4. Mapping TM Learning Element to Y-Flash Cell
  5. Experiment and Results
  6. Conclusion

Figures (7)

  • Figure 1: Learning Tsetlin Automaton based on a Y-Flash device. (a) Visual representation of the Y-Flash device. (b) Connection of the two sources to form a dual-terminal setup. Demonstrating the device's pronounced self-selection capability through a low positive voltage application. The device state is determined by the current under positive bias (VDS = 2V). (c) Tsetlin Automaton FSM.
  • Figure 2: The DC IV characteristics of a Y-FLASH device during a reading pulse ($V_D$ = 2V) exhibit distinct behaviors based on its conductance state: (a) In the low conductance state, $I_D$ is $\approx$1nA, and (b) in the high conductance state, $I_D$ increases significantly to $\approx$ 5$\mu$A.
  • Figure 3: Multi-conductance states achieved through repeated pulses. (a) and (c) $I_D$ vs. $V_D$ for programming and erasing, respectively. (b) and (d) Conductance (at $V_R = 2V$) change with pulse number for programming and erasing, respectively.
  • Figure 4: The framework of mimic the TA state transition.
  • Figure 5: (a) State transitions of eight TAs during the learning procedure. (b) Writing cycles of the eight corresponding Y-Flash cells associated with the TAs.
  • ...and 2 more figures