VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

TL;DR

This work tackles the difficulty of automatically generating correct Verilog hardware descriptions by introducing VerilogCoder, a multi-AI agent system that combines a novel Task and Circuit Relation Graph (TCRG) planner with an AST-based waveform tracing tool to debug both syntax and functionality. The approach orchestrates specialized agents across planning, signal extraction, and Verilog code generation, leveraging collaborative Verilog tools (syntax checker, simulator, and AST-WT) to iteratively refine code. Key contributions include the first large-scale use of multi-AI agents for autonomous Verilog coding, the TCRG-based planning framework for signal-aware sub-tasks, and the AST-WT for functional debugging, backed by extensive ablation studies on the VerilogEval-Human v2 benchmark that yield a 94.2% pass rate and substantial improvements over state-of-the-art methods. The results demonstrate a viable path toward autonomous hardware design assistance, reducing design iterations and enabling more reliable Verilog code generation in complex IC workflows.

Abstract

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

Figures (5)

• Figure 1: Illustrations of (a) traditional LLM planning versus TCRG based planning, and (b) human Verilog designer debugging process and AST signal back tracing in Motivation and Preliminary Study section.
• Figure 2: Flow overview of VerilogCoder. (a) Overall flow for Verilog code implementation task. (b) LLM roles of multi-LLM agents. (c) Multi-LLM agents in Task Planning. (d) Multi-LLM Agents for sub-tasks in Verilog Code Implementation.
• Figure 3: An illustration of task-driven circuit relation graph retrieval agent reasoning and interacting with the developed TCRG retrieval tool to enrich the task with the relevant circuit and signal descriptions.
• Figure 4: An example of Debug Agent reasoning and interacting with simulator and AST-based waveform tracing tool.
• Figure 5: Taxonomy study results. (a) The statistics of extracted failed problems set and the number of problems in each module and query prompt type category. (b) Pass-rate (%) of each module and query prompt type categories.