Cross-Chip Partial Reconfiguration for the Initialisation of Modular and Scalable Heterogeneous Systems

TL;DR

This paper addresses initializing and updating peripheral FPGAs in modular heterogeneous systems by leveraging cross-chip partial reconfiguration over AXI C2C. It proposes a Linux-based workflow using the FPGA subsystem, fpga managers/bridges, and device-tree overlays to initialize and reconfigure external FPGAs via icap. The approach uses a central rfsoc and per-device management with a 3-stage initialisation and 40-bit addressing scheme to enable scalable expansion. Evaluation across three setups shows up to 178 MB/s reconfiguration throughput with hbicap on AXI4, demonstrating practical viability for startup and runtime updates in multi-device QiController architectures, with room for further improvement through custom icap/cdma controllers.

Abstract

The almost unlimited possibilities to customize the logic in an FPGA are one of the main reasons for the versatility of these devices. Partial reconfiguration exploits this capability even further by allowing to replace logic in predefined FPGA regions at runtime. This is especially relevant in heterogeneous SoCs, combining FPGA fabric with conventional processors on a single die. Tight integration and supporting frameworks like the FPGA subsystem in Linux facilitate use, for example, to dynamically load custom hardware accelerators. Although this example is one of the most common use cases for partial reconfiguration, the possible applications go far beyond. We propose to use partial reconfiguration in combination with the AXI C2C cross-chip bus to extend the resources of heterogeneous MPSoC and RFSoC devices by connecting peripheral FPGAs. With AXI C2C it is easily possible to link the programmable logic of the individual devices, but partial reconfiguration on peripheral FPGAs utilising the same channel is not officially supported. By using an AXI ICAP controller in combination with custom Linux drivers, we show that it is possible to enable the PS of the heterogeneous SoC to perform partial reconfiguration on peripheral FPGAs, and thus to seamlessly access and manage the entire multi-device system. As a result, software and FPGA firmware updates can be applied to the entire system at runtime, and peripheral FPGAs can be added and removed during operation.

Figures (9)

• Figure 1: Proposed modular and scalable multi-device QiController architecture. All connections between atca blades are established via the atca backplane.
• Figure 2: Resource extension of an mpsoc using a peripheral fpga connected via axi c2c, utilizing gt on both devices. For both the pl of the mpsoc and for the fpga, the most important configuration interfaces are shown. The interfaces that are to be used in the multi-device QiController are highlighted (pcap to configure the pl in the mpsoc, icap to configure the peripheral fpga).
• Figure 3: Setup with one AMD Xilinx ZCU102 and one AMD Xilinx VCU118 to test cross-chip pr with a basic fpga firmware architecture.
• Figure 4: Setup with one AMD Xilinx ZCU102 and one AMD Xilinx VCU118 to test the performance of cross-chip pr via a full AXI4 interface. The hbicap IP core used features an AXI4-Lite control interface and an AXI4 data interface.
• Figure 5: Setup with one AMD Xilinx ZCU102 to test the performance of the combination of hbicap and cdma without axi c2c.