Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

TL;DR

This paper addresses the misalignment between logic synthesis and physical design by introducing PigMAP, a framework that uses primitive logic gate placement to derive approximate spatial cues for wirelength-driven technology mapping. It presents a dual-mode mapping strategy—PigMAP-Performance and PigMAP-Power—that trade off critical-path delay against total wirelength to improve post-routing PPA. By integrating a placement-aware mapper with a fast placer and introducing the novel virtual wirelength metric, PigMAP achieves PD-friendly netlists and demonstrably improves delay and/or power in EPFL ASAP7 OpenROAD flows. The approach demonstrates the value of shifting physically informed decisions earlier in the design flow, enabling more predictable and efficient convergence to timing closure.

Abstract

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption.

Figures (8)

• Figure 1: The challenges associated with physically aware synthesis methodology. In design AES 05IWLS_albrecht_iwls, the Y-axis shows the ratio of critical path delay, while the X-axis shows the iteration steps, including five rounds of logic optimization, global placement, detailed placement and detailed routing.
• Figure 2: Different physically aware synthesis flows.
• Figure 3: The PigMAP framework of ASIC design.
• Figure 4: An example for AIG placement of C17.
• Figure 5: An example of searching pins of node $8$. For node $8$, two different cuts are identified: {$2,7$} and {$2,3,4$}. Each cut has associated pins: the cut {$2,7$} is associated with the pin {$8$} and the cut {$2,3,4$} has pins {$7,8$}.

Theorems & Definitions (4)

• Definition 1
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• Definition 4