Analog Spiking Neuron in CMOS 28 nm Towards Large-Scale Neuromorphic Processors

TL;DR

This paper demonstrates a low-power analog Leaky Integrate-and-Fire neuron implemented in 28 nm CMOS as a building block for scalable neuromorphic processors. It combines hardware fabrication data (1.61 fJ per spike, ~34 μm² active area, up to 300 kHz at 250 mV) with a software model that emulates the analog LIF to train a Spiking Neural Network on MNIST using surrogate-gradient backpropagation and 4-bit post-training quantization, achieving 82.5% accuracy. The work validates both the hardware’s energy efficiency and its applicability to large-scale neuromorphic systems, supported by a PyTorch-based emulation framework and a careful energy-per-spike analysis. Overall, it supports the feasibility of compact, energy-efficient NeuroSoCs by combining analog CMOS LIF neurons with quantized SNN software modeling for edge AI applications.

Abstract

The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms. In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC's 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 $μm^{2}$, leading to a maximum spiking frequency of 300 kHz at 250 mV power supply. These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit post-training quantization stands at 82.5\%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications.

Figures (14)

• Figure 1: Proposed neuron circuit in CMOS. $M_{1}$-$M_{2}$-$C_{mem}$: Integration block; $M_{3}$-$M_{4}$-$C_{res}$: Reset block; $M_{5}$-$M_{8}$: Spike generation block.
• Figure 2: LIF neuron layout for implementation in TSMC 28 nm CMOS.
• Figure 3: Experimental Setup featuring the measurement equipment and the printed circuit board test bench custom designed for the chip.
• Figure 4: Internal probing buffer for the output signals of the chip. Namely the membrane integration signal and the spiking signal.
• Figure 5: Simplified illustration of the experimental setup used to study the integration of synaptic current $I_{syn}$ in membrane capacitor $C_{mem}$ of the implemented analog LIF neuron.