Embodied Biocomputing Sequential Circuits with Data Processing and Storage for Neurons-on-a-chip

TL;DR

This study explores the potential of neuronal biocomputing to rival silicon-based systems by exploring neuronal logic gates and sequential circuits that mimic conventional computer architectures and establishes the foundation for cutting-edge biocomputing technologies.

Abstract

With conventional silicon-based computing approaching its physical and efficiency limits, biocomputing emerges as a promising alternative. This approach utilises biomaterials such as DNA and neurons as an interesting alternative to data processing and storage. This study explores the potential of neuronal biocomputing to rival silicon-based systems. We explore neuronal logic gates and sequential circuits that mimic conventional computer architectures. Through mathematical modelling, optimisation, and computer simulation, we demonstrate the operational capabilities of neuronal sequential circuits. These circuits include a neuronal NAND gate, SR Latch flip-flop, and D flip-flop memory units. Our approach involves manipulating neuron communication, synaptic conductance, spike buffers, neuron types, and specific neuronal network topology designs. The experiments demonstrate the practicality of encoding binary information using patterns of neuronal activity and overcoming synchronization difficulties with neuronal buffers and inhibition strategies. Our results confirm the effectiveness and scalability of neuronal logic circuits, showing that they maintain a stable metabolic burden even in complex data storage configurations. Our study not only demonstrates the concept of embodied biocomputing by manipulating neuronal properties for digital signal processing but also establishes the foundation for cutting-edge biocomputing technologies. Our designs open up possibilities for using neurons as energy-efficient computing solutions. These solutions have the potential to become an alternate to silicon-based systems by providing a carbon-neutral, biologically feasible alternative.

Figures (4)

• Figure 1: Gating response of the neuronal AND and AND NOT gates. a) The logic gate formal symbolic representation of the AND and below its truth table b) the functional graph of the neurons and connections, including types, composing the AND gate c) the functional validation of the AND gate following the truth table order in a) d) the time-series metabolic burden per neuronal unit e) The logic gate formal symbolic representation of the AND NOT and below its truth table f) the functional graph of the neurons and connections, including types, composing the AND NOT gate g) the functional validation of the AND NOT gate following the truth table order in e) h) the time-series metabolic burden per neuronal unit. For the excitatory synapse, the synaptic parameters are set as: $w_x=0.06$, $\tau_r=19.80$ ms and $\tau_d=26.40$ ms. For the inhibitory synapse, they are chosen as: $w_y=0.18$, $\tau_r=19.80$ ms and $\tau_d=59.40$ ms. The amplitude of the stimulating current is $I=4$ pA. (a-h)
• Figure 2: Gating response of the neuronal NOT and NAND gates. a) The logic gate formal symbolic representation of the NOT and below its truth table b) the functional graph of the neurons and connections, including types, composing the NOT gate c) the functional validation of the NOT gate following the truth table order in a) d) the time-series metabolic burden per neuronal unit e) The logic gate formal symbolic representation of the NAND and below its truth table f) the functional graph of the neurons and connections, including types, composing the NAND gate g) the functional validation of the NAND gate following the truth table order in e) h) the time-series metabolic burden per neuronal unit. For the excitatory synapse, the synaptic parameters are set as: $w_x=0.06$, $\tau_r=19.80$ ms and $\tau_d=26.40$ ms. For the inhibitory synapse, they are chosen as: $w_y=0.18$, $\tau_r=19.80$ ms and $\tau_d=59.40$ ms. The amplitude of the stimulating current is $I=4$ pA. Gating response of the neuronal NAND gate. The synaptic parameters of the AND gate are $w_z=0.065$, $\tau_r=2.64$ ms and $\tau_d=3.96$ ms; for the NOT gate excitatory synapse $w_x=0.06$, $\tau_r=19.80$ ms and $\tau_d=26.40$ ms; for the NOT gate inhibitory synapse $w_y=0.18$, $\tau_r=19.80$ ms and $\tau_d=59.40$ ms. The amplitude of the stimulating current is $I=4$ pA. (a-h)
• Figure 3: Gating response of the neuronal SR latch and GATED SR latch, with stimulating current $I=4$ pA. a) The logic gate formal symbolic representation of the SR latch and below its truth table b) the functional graph of the neurons and connections, including types, composing the SR latch c) the functional validation of the SR latch following the truth table order in a) d) the time-series metabolic burden per neuronal unit e) The logic gate formal symbolic representation of the GATED SR latch and below its truth table f) the functional graph of the neurons and connections, including types, composing the GATED SR latch g) the functional validation of the GATED SR latch following the truth table order in e) h) the time-series metabolic burden per neuronal unit.
• Figure 4: Gating response of the neuronal flip-flop and D flip-flop with stimulating current $I=4$ pA and $I=7$ pA. a) symbolic representation of the flip-flop b) the symbolic representation of the D flip-flop c) the time series burden of the D flip-flop inputs and output neuronal units with $I=4$ pA d) the time series burden of the D flip-flop inputs and output neuronal units with $I=7$ pA e) the functional validation of the D flip-flop inputs D and CLK and outputs Q and $\overline{Q}$ with $I=4$ pA f) the functional validation of the D flip-flop inputs D and CLK and outputs Q and $\overline{Q}$ with $I=7$ pA g) the functional graph of the neurons and connections, including types, composing the D flip-flop.