Optimization-Based Model Checking and Trace Synthesis for Complex STL Specifications
Sota Sato, Jie An, Zhenya Zhang, Ichiro Hasuo
TL;DR
The paper addresses bounded trace synthesis and model checking for Signal Temporal Logic (STL) specifications in cyber-physical systems by restricting to MILP-encodable, white-box models. It introduces a variable-interval STL encoding and a delta-stable partitioning framework that yields an optimization-based, anytime MILP formulation for finding traces that satisfy the spec or proving infeasibility. Core contributions include the delta-stable partitioning concept, a complete MILP encoding of STL with both Boolean and temporal operators, and exact/approximate MILP encodings for Rectangular Hybrid Automata and double-integrator dynamics, respectively, enabling scalable automotive-style analyses and parameter mining. The approach is implemented in STLts and validated on automotive-like benchmarks (RNC, NAV, ISO disturbance scenarios), showing improved performance over falsification and SMT-based methods and demonstrating practical applicability for spec analysis in CPS design.
Abstract
We present a bounded model checking algorithm for signal temporal logic (STL) that exploits mixed-integer linear programming (MILP). A key technical element is our novel MILP encoding of the STL semantics; it follows the idea of stable partitioning from the recent work on SMT-based STL model checking. Assuming that our (continuous-time) system models can be encoded to MILP -- typical examples are rectangular hybrid automata (precisely) and hybrid dynamics with closed-form solutions (approximately) -- our MILP encoding yields an optimization-based model checking algorithm that is scalable, is anytime/interruptible, and accommodates parameter mining. Experimental evaluation shows our algorithm's performance advantages especially for complex STL formulas, demonstrating its practical relevance e.g. in the automotive domain.
