Understanding Power Consumption Metric on Heterogeneous Memory Systems

TL;DR

This paper tackles the challenge of power consumption in heterogeneous memory systems (HMS) for high-performance computing. It proposes a methodology to quantify the power usage of individual memory types and to produce an ordering of memories tailored to applications. By employing topology-aware binding, memory-bound benchmarks, and counters from PCM and perf tools, it demonstrates how power profiles can vary across DRAM, NVM, and emulated memory types, and shows that the optimal memory choice is application- and HMS-dependent. The findings enable developers to craft power-aware memory profiles, improving energy efficiency while maintaining or balancing performance across diverse HPC workloads.

Abstract

Contemporary memory systems contain a variety of memory types, each possessing distinct characteristics. This trend empowers applications to opt for memory types aligning with developer's desired behavior. As a result, developers gain flexibility to tailor their applications to specific needs, factoring in attributes like latency, bandwidth, and power consumption. Our research centers on the aspect of power consumption within memory systems. We introduce an approach that equips developers with comprehensive insights into the power consumption of individual memory types. Additionally, we propose an ordered hierarchy of memory types. Through this methodology, developers can make informed decisions for efficient memory usage aligned with their unique requirements.

Figures (3)

• Figure 1: Memory-Storage Continuum.
• Figure 2: Emulation by binding application process to a remote memory target.
• Figure 3: Memory power consumption behavior taking into account the number of threads on executions bound to Local DRAM, Local NVM, and Remote DRAM.