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Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment

Yuxuan Yin, Rebecca Chen, Chen He, Peng Li

TL;DR

The paper tackles predicting the minimum operating voltage $V_{min}$ under complex wafer-to-wafer and intra-wafer process variations. It introduces restricted bias alignment (RBA), a data-efficient framework that decouples inter- and intra-wafer shifts and leverages class-probe features to model inter-wafer variation, with BA as a baseline alignment method. Through extensive experiments on thousands of 16nm automotive chips, RBA demonstrates improved accuracy over standard linear regression and exhibits strong data efficiency and deployability to new wafers, particularly for MBST $V_{min}$ predictions. This approach enhances manufacturing reliability and testing efficiency by robustly accounting for variation sources without excessive retraining or measurement overhead.

Abstract

Predicting the minimum operating voltage ($V_{min}$) of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing $V_{min}$ prediction methods often overlook various sources of variations in both training and deployment phases. Notably, the neglect of wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations, compounded by process variations, diminishes the accuracy, data efficiency, and reliability of $V_{min}$ predictors. To address this gap, we introduce a novel data-efficient $V_{min}$ prediction flow, termed restricted bias alignment (RBA), which incorporates a novel variation alignment technique. Our approach concurrently estimates inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time. We empirically demonstrate RBA's effectiveness and data efficiency on an industrial 16nm automotive chip dataset.

Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment

TL;DR

The paper tackles predicting the minimum operating voltage under complex wafer-to-wafer and intra-wafer process variations. It introduces restricted bias alignment (RBA), a data-efficient framework that decouples inter- and intra-wafer shifts and leverages class-probe features to model inter-wafer variation, with BA as a baseline alignment method. Through extensive experiments on thousands of 16nm automotive chips, RBA demonstrates improved accuracy over standard linear regression and exhibits strong data efficiency and deployability to new wafers, particularly for MBST predictions. This approach enhances manufacturing reliability and testing efficiency by robustly accounting for variation sources without excessive retraining or measurement overhead.

Abstract

Predicting the minimum operating voltage () of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing prediction methods often overlook various sources of variations in both training and deployment phases. Notably, the neglect of wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations, compounded by process variations, diminishes the accuracy, data efficiency, and reliability of predictors. To address this gap, we introduce a novel data-efficient prediction flow, termed restricted bias alignment (RBA), which incorporates a novel variation alignment technique. Our approach concurrently estimates inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time. We empirically demonstrate RBA's effectiveness and data efficiency on an industrial 16nm automotive chip dataset.
Paper Structure (31 sections, 24 equations, 5 figures, 10 tables)

This paper contains 31 sections, 24 equations, 5 figures, 10 tables.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Testing Flow in Semiconductor Manufacturing
  4. Linear Regression for $V_{min}$ Prediction
  5. Influence of Inter- and Intra-Wafer Variation on $V_{min}$ Prediction
  6. Data Efficient Inter- and Intra-Wafer Variation Alignment
  7. Bias Alignment (BA) for $V_{min}$ Prediction
  8. Problem Formulation
  9. Solution
  10. Discussion
  11. Restricted Bias Alignment (RBA) for $V_{min}$ Prediction
  12. Problem Formulation
  13. Solution
  14. Discussion
  15. Experimental Results
  16. ...and 16 more sections

Figures (5)

  • Figure 1: Wafer-to-wafer and wafer zone variations across 2 wafers, measured at 25° C. Red dashed lines represent mean values.
  • Figure 2: Class probe test structures and process observation structures
  • Figure 3: A highly-parallel wafer probe touchdown
  • Figure 4: A balanced wafer region partition into 4 regions
  • Figure 5: Variation of testing residuals of $V_{min}$ prediction of a linear regression trained on dies from the center zone from wafer 1. Red dashed lines represent mean values.