Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutation
Irfansha Shaik, Jaco van de Pol
TL;DR
This work tackles optimal CNOT circuit synthesis under two practical extensions: qubit permutation and hardware layout restrictions. It introduces four synthesis variants (S, S+R, W, W+R) and provides optimal encodings for Planning, SAT, and QBF, with single- and parallel-time formulations for gate- and depth-optimization. Empirical results on standard T-gate benchmarks show that allowing qubit permutation can substantially reduce CNOT counts and circuit depth, while layout restrictions yield additional gains when combined with permutation. The study delivers the first known optimal encodings for W and W+R, demonstrates peephole optimization, and provides an open-source tool Q-Synth v3 to enable broader adoption and comparison in quantum circuit compilation pipelines.
Abstract
CNOT optimization plays a significant role in noise reduction for Quantum Circuits. Several heuristic and exact approaches exist for CNOT optimization. In this paper, we investigate more complicated variations of optimal synthesis by allowing qubit permutations and handling layout restrictions. We encode such problems into Planning, SAT, and QBF. We provide optimization for both CNOT gate count and circuit depth. For experimental evaluation, we consider standard T-gate optimized benchmarks and optimize CNOT sub-circuits. We show that allowing qubit permutations can further reduce up to 56% in CNOT count and 46% in circuit depth. In the case of optimally mapped circuits under layout restrictions, we observe a reduction up to 17% CNOT count and 19% CNOT depth.