C-Nash: A Novel Ferroelectric Computing-in-Memory Architecture for Solving Mixed Strategy Nash Equilibrium

TL;DR

This paper addresses the challenge of solving mixed-strategy Nash Equilibria by introducing C-Nash, a ferroelectric computing-in-memory architecture. It replaces lossy Slack-QUBO mappings with a lossless MAX-QUBO transformation and leverages FeFET-based crossbars, a Winner-Takes-All tree, and a two-phase simulated annealing controller to search NE solutions. Key contributions include the MAX-QUBO lossless transformation (α = max(Mq), β = max(N^T p)), an FeFET bi-crossbar mapping for VMV multiplications, and an integrated SA flow that efficiently finds both pure and mixed NE with high success rates. The approach yields significantly higher NE discovery rates and substantially faster time-to-solution than D-Wave quantum solvers, demonstrating the practical viability of CiM-based approaches for game-theoretic computation.

Abstract

The concept of Nash equilibrium (NE), pivotal within game theory, has garnered widespread attention across numerous industries. Recent advancements introduced several quantum Nash solvers aimed at identifying pure strategy NE solutions (i.e., binary solutions) by integrating slack terms into the objective function, commonly referred to as slack-quadratic unconstrained binary optimization (S-QUBO). However, incorporation of slack terms into the quadratic optimization results in changes of the objective function, which may cause incorrect solutions. Furthermore, these quantum solvers only identify a limited subset of pure strategy NE solutions, and fail to address mixed strategy NE (i.e., decimal solutions), leaving many solutions undiscovered. In this work, we propose C-Nash, a novel ferroelectric computing-in-memory (CiM) architecture that can efficiently handle both pure and mixed strategy NE solutions. The proposed architecture consists of (i) a transformation method that converts quadratic optimization into a MAX-QUBO form without introducing additional slack variables, thereby avoiding objective function changes; (ii) a ferroelectric FET (FeFET) based bi-crossbar structure for storing payoff matrices and accelerating the core vector-matrix-vector (VMV) multiplications of QUBO form; (iii) A winner-takes-all (WTA) tree implementing the MAX form and a two-phase based simulated annealing (SA) logic for searching NE solutions. Evaluations show that C-Nash has up to 68.6% increase in the success rate for identifying NE solutions, finding all pure and mixed NE solutions rather than only a portion of pure NE solutions, compared to D-Wave based quantum approaches. Moreover, C-Nash boasts a reduction up to 157.9X/79.0X in time-to-solutions compared to D-Wave 2000 Q6 and D-Wave Advantage 4.1, respectively.

Figures (10)

• Figure 1: Existing approaches for addressing NE. (a) The Slack-QUBO conversion (S-QUBO) performs a lossy transformation to handle inequalities at the cost of extra slack variables; (b) S-QUBO based quantum annealers, such as D-Wave, solve only limited type of NE.
• Figure 2: (a) FeFET can be programmed to store low/high $V_\text{TH}$ by applying different write pulses; (b) I$_D$-V$_G$ characteristics of FeFET storing binary state $m_i$; (c) The 1FeFET1R structure storing binary $m_i$ naturally performs $i = p\times m_i \times q$ through its drain-source current $i$ by applying two inputs $p$ and $q$ at the gate $WL$ and drain $DL$, respectively, and leveraging (d) the I$_D$-V$_G$ characteristics with suppressed ON current variability.
• Figure 3: Overview of C-Nash. (a) MAX-QUBO transformation; (b), (c) FeFET-based bi-crossbar structure; (d) Winner-takes-all (WTA) tree; (e) Two-phase based simulated annealing (SA) logic.
• Figure 4: Mapping strategy of bi-crossbar. (a) A FeFET based crossbar implementing $p\times M \times q$ with strategy inputs quantified to $I$ intervals and each element of $M$ represented by $t$ cells; (b) Subarray implementing scalar multiplications $p_1\times M_{11} \times q_1$; (c) A mapping example of $0.25\times 3 \times 0.75$ with $I=4$ and $t=4$.
• Figure 5: (a) Diagram of a WTA tree; (b) Schematic of a 2-input WTA cell; (c) Transient waveforms of a WTA cell.