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Solving QUBO on the Loihi 2 Neuromorphic Processor

Alessandro Pierro, Philipp Stratmann, Gabriel Andres Fonseca Guerra, Sumedh Risbud, Timothy Shea, Ashish Rao Mangalore, Andreas Wild

TL;DR

An algorithm for solving Quadratic Unconstrained Binary Optimization problems on the Intel Loihi 2 neuromorphic processor based on a hardware-aware fine-grained parallel simulated annealing algorithm developed for Intel's neuromorphic research chip Loihi 2.

Abstract

In this article, we describe an algorithm for solving Quadratic Unconstrained Binary Optimization problems on the Intel Loihi 2 neuromorphic processor. The solver is based on a hardware-aware fine-grained parallel simulated annealing algorithm developed for Intel's neuromorphic research chip Loihi 2. Preliminary results show that our approach can generate feasible solutions in as little as 1 ms and up to 37x more energy efficient compared to two baseline solvers running on a CPU. These advantages could be especially relevant for size-, weight-, and power-constrained edge computing applications.

Solving QUBO on the Loihi 2 Neuromorphic Processor

TL;DR

An algorithm for solving Quadratic Unconstrained Binary Optimization problems on the Intel Loihi 2 neuromorphic processor based on a hardware-aware fine-grained parallel simulated annealing algorithm developed for Intel's neuromorphic research chip Loihi 2.

Abstract

In this article, we describe an algorithm for solving Quadratic Unconstrained Binary Optimization problems on the Intel Loihi 2 neuromorphic processor. The solver is based on a hardware-aware fine-grained parallel simulated annealing algorithm developed for Intel's neuromorphic research chip Loihi 2. Preliminary results show that our approach can generate feasible solutions in as little as 1 ms and up to 37x more energy efficient compared to two baseline solvers running on a CPU. These advantages could be especially relevant for size-, weight-, and power-constrained edge computing applications.
Paper Structure (18 sections, 16 equations, 3 figures, 2 tables)

This paper contains 18 sections, 16 equations, 3 figures, 2 tables.

Table of Contents

  1. Abstract
  2. Introduction
  3. Hardware-aware simulated annealing
  4. Benchmarking methods
  5. Benchmarking results
  6. Discussion
  7. Acknowledgments
  8. Author Contributions
  9. Competing Interests

Figures (3)

  • Figure 1: Diagram for the proposed QUBO neural architecture: the variable neurons are recursively connected by a layer of synapses (in blue), which encode the coefficients of the Q matrix, and to the cost integrator by synapses with unit weights (in red).
  • Figure 2: Percentage gap from the best known solution for the MIS instances ($15\%$ density), for increasing timeout values.
  • Figure 3: Power consumption running the MIS instances with the different solvers. The CPU solvers require up to $37\times$ more power than our neuromorphic SA on Loihi 2.