Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools

TL;DR

This paper investigates implementing Finite-Time Lyapunov Exponent (FTLE) calculations on Xilinx FPGAs using High-Level Synthesis (Vitis HLS). It shows that naïve porting of FTLE is often不可 synthesize efficiently due to memory bottlenecks, and that a memory-aware approach—comprising precomputed neighbor indices and a regular access pattern—enables deeper pipelining and higher throughput. The study demonstrates that the floating-point FTLE core can achieve GFLOPS-scale performance (about 24.6 GFLOPS for 2D and 61.8 GFLOPS for 3D) when memory bandwidth is effectively utilized, with HBM offering the best prospects. The work highlights the importance of memory architecture and data layout for FPGA accelerators and outlines future work to validate on hardware and further optimize data management, including neighbor-list generation and HBM usage.

Abstract

As Field Programmable Gate Arrays (FPGAs) computing capabilities continue to grow, also does the interest on building scientific accelerators around them. Tools like Xilinx's High-Level Synthesis (HLS) help to bridge the gap between traditional high-level languages such as C and C++, and low-level hardware description languages such as VHDL and Verilog. In this report, we study the implementation of a fluid dynamics application, the Finite-Time Lyapunov Exponent (FTLE) calculation, on FPGA using HLS. We provide speed and resource-consumption results for 2- and 3-dimensional cases.