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HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine

Omkar Kokane, Prabhat Sati, Mukul Lokhande, Santosh Kumar Vishvakarma

TL;DR

This work introduces the Hybrid Overestimating Approximate Adder (HOAA) and its constituent Plus One Adder (P1A) to accelerate edge-AI processing engines by trading a small amount of accuracy for substantial hardware efficiency. P1A replaces the LSBs in a Ripple Carry Adder with a compact, excess-1 capable block, enabling a single-cycle +1 operation while supporting a reconfigurable mode that switches between accurate and approximate addition. The architecture is validated on 8-bit designs with CMOS 28nm synthesis and Monte Carlo error analysis, showing about 21% area reduction and 33% power reduction relative to state-of-the-art adds, with minimal accuracy loss across subtraction, rounding-to-even, and configurable activation function scenarios. This approach enables more energy-efficient, high-throughput edge-AI accelerators and can be extended to integrate with underestimating approximate multipliers for further gains.

Abstract

This paper presents the Hybrid Overestimating Approximate Adder designed to enhance the performance in processing engines, specifically focused on edge AI applications. A novel Plus One Adder design is proposed as an incremental adder in the RCA chain, incorporating a Full Adder with an excess 1 alongside inputs A, B, and Cin. The design approximates outputs to 2 bit values to reduce hardware complexity and improve resource efficiency. The Plus One Adder is integrated into a dynamically reconfigurable HOAA, allowing runtime interchangeability between accurate and approximate overestimation modes. The proposed design is demonstrated for multiple applications, such as Twos complement subtraction and Rounding to even, and the Configurable Activation function, which are critical components of the Processing engine. Our approach shows 21 percent improvement in area efficiency and 33 percent reduction in power consumption, compared to state of the art designs with minimal accuracy loss. Thus, the proposed HOAA could be a promising solution for resource-constrained environments, offering ideal trade-offs between hardware efficiency vs computational accuracy.

HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine

TL;DR

This work introduces the Hybrid Overestimating Approximate Adder (HOAA) and its constituent Plus One Adder (P1A) to accelerate edge-AI processing engines by trading a small amount of accuracy for substantial hardware efficiency. P1A replaces the LSBs in a Ripple Carry Adder with a compact, excess-1 capable block, enabling a single-cycle +1 operation while supporting a reconfigurable mode that switches between accurate and approximate addition. The architecture is validated on 8-bit designs with CMOS 28nm synthesis and Monte Carlo error analysis, showing about 21% area reduction and 33% power reduction relative to state-of-the-art adds, with minimal accuracy loss across subtraction, rounding-to-even, and configurable activation function scenarios. This approach enables more energy-efficient, high-throughput edge-AI accelerators and can be extended to integrate with underestimating approximate multipliers for further gains.

Abstract

This paper presents the Hybrid Overestimating Approximate Adder designed to enhance the performance in processing engines, specifically focused on edge AI applications. A novel Plus One Adder design is proposed as an incremental adder in the RCA chain, incorporating a Full Adder with an excess 1 alongside inputs A, B, and Cin. The design approximates outputs to 2 bit values to reduce hardware complexity and improve resource efficiency. The Plus One Adder is integrated into a dynamically reconfigurable HOAA, allowing runtime interchangeability between accurate and approximate overestimation modes. The proposed design is demonstrated for multiple applications, such as Twos complement subtraction and Rounding to even, and the Configurable Activation function, which are critical components of the Processing engine. Our approach shows 21 percent improvement in area efficiency and 33 percent reduction in power consumption, compared to state of the art designs with minimal accuracy loss. Thus, the proposed HOAA could be a promising solution for resource-constrained environments, offering ideal trade-offs between hardware efficiency vs computational accuracy.
Paper Structure (10 sections, 6 equations, 4 figures, 4 tables)

This paper contains 10 sections, 6 equations, 4 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Proposed Architecture
  4. Proposed P1A Design
  5. Proposed HOAA Design
  6. Methodology & Results Discussion
  7. Case-I: Subtraction
  8. Case-II: Rounding-to-even
  9. Case-III: Configurable activation function
  10. Conclusion

Figures (4)

  • Figure 1: Classic 2D systolic array architecture with PE highlighting the regions to be improved
  • Figure 2: N - Bit Re-Configurable Adder, (n+1) bit HOAA
  • Figure 3: 1-bit Schematic of a) Conventional Full Adder b) Plus One Adder
  • Figure 4: Comparison for Maximum Operating Frequency