Machine Learning In-Sensors: Computation-enabled Intelligent Sensors For Next Generation of IoT

TL;DR

The paper tackles enabling AI inference directly on ultra-low-power edge sensors to reduce data transmission, latency, and privacy concerns. It evaluates the STMicroelectronics ISPU integrated in the ISM330AILP inertial sensor for on-sensor feature extraction and neural networks, comparing full-precision and binary nets on an activity-recognition task. Results indicate that full-precision networks run on the ISPU with performance comparable to a Cortex-M4, while large binary networks achieve substantial speedups when using the dedicated BNN accelerator, with low energy per inference. This work demonstrates the practicality of computation-enabled intelligent sensors for next-generation IoT, enabling low-latency, energy-efficient edge analytics directly on the sensor.

Abstract

Smart sensors are an emerging technology that allows combining the data acquisition with the elaboration directly on the Edge device, very close to the sensors. To push this concept to the extreme, technology companies are proposing a new generation of sensors allowing to move the intelligence from the edge host device, typically a microcontroller, directly to the ultra-low-power sensor itself, in order to further reduce the miniaturization, cost and energy efficiency. This paper evaluates the capabilities of a novel and promising solution from STMicroelectronics. The presence of a floating point unit and an accelerator for binary neural networks provide capabilities for in-sensor feature extraction and machine learning. We propose a comparison of full-precision and binary neural networks for activity recognition with accelerometer data generated by the sensor itself. Experimental results have demonstrated that the sensor can achieve an inference performance of 10.7 cycles/MAC, comparable to a Cortex-M4-based microcontroller, with full-precision networks, and up to 1.5 cycles/MAC with large binary models for low latency inference, with an average energy consumption of only 90 $μ$J/inference with the core running at 5 MHz.

Figures (3)

• Figure 1: High-level block diagram of the ISM330AILP
• Figure 2: Graphical representation of our classification pipeline. The network architecture is not representative.
• Figure 3: Execution time of different models on the ISM330AILP