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Functional ISS-Driven Verification of Superscalar RISC-V Processors

Andrea Galimberti, Marco Vitali, Sebastiano Vittoria, Davide Zoni

TL;DR

The paper tackles the need for fast, accurate functional verification of superscalar RISCV processors as cores grow more complex. It proposes SupeRFIVe, a socket-based ISS-driven verification flow that runs the same executable on both a DUT in SystemVerilog and the Spike RISC-V ISA simulator, synchronizing at the level of committed instructions. The approach enables immediate detection of mismatches in registers and memory and collects metrics such as instruction throughput and ILP indicators during verification. Experimental validation on a RV32IMF dual-issue core using WCET benchmarks demonstrates correct functionality and reveals meaningful ILP statistics, including a substantial fraction of concurrent commits. The methodology provides a practical, scalable alternative to slower cycle-accurate simulators for functional verification of modern RISCV superscalar designs.

Abstract

A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature.

Functional ISS-Driven Verification of Superscalar RISC-V Processors

TL;DR

The paper tackles the need for fast, accurate functional verification of superscalar RISCV processors as cores grow more complex. It proposes SupeRFIVe, a socket-based ISS-driven verification flow that runs the same executable on both a DUT in SystemVerilog and the Spike RISC-V ISA simulator, synchronizing at the level of committed instructions. The approach enables immediate detection of mismatches in registers and memory and collects metrics such as instruction throughput and ILP indicators during verification. Experimental validation on a RV32IMF dual-issue core using WCET benchmarks demonstrates correct functionality and reveals meaningful ILP statistics, including a substantial fraction of concurrent commits. The methodology provides a practical, scalable alternative to slower cycle-accurate simulators for functional verification of modern RISCV superscalar designs.

Abstract

A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature.
Paper Structure (6 sections, 3 figures, 1 table)

This paper contains 6 sections, 3 figures, 1 table.

Table of Contents

  1. Introduction
  2. SupeRFIVe Methodology
  3. Experimental results
  4. Experimental setup
  5. Experimental results
  6. Conclusions

Figures (3)

  • Figure 1: Flowchart of the SupeRFIVe methodology.
  • Figure 2: Verification infrastructure that implements the proposed SupeRFIVe methodology for experimental evaluation purposes.
  • Figure 3: Fraction of double commits when executing the Mälardalen WCET applications in \ref{['tab:statistics']} on the target superscalar CPU. Labels inside the stacked columns refer to the number of double and single commits.