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Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic

Jennifer Volk, Panagiotis Papanikolaou, Georgios Zervakis, Georgios Tzimpragos

TL;DR

The paper tackles the challenge of clocked synthesis in superconducting SFQ circuits by introducing clock-free xSFQ logic with dual-rail alternating encoding, enabling complete design automation without clock distribution. It develops a complete xSFQ standard cell library (LA/FA at $4$ JJs, DROC storage with $4$-JJ preloading, and characterization data) and links xSFQ to AIG/domino optimizations to aggressively reduce resource usage. The authors demonstrate a comprehensive RTL-to-xSFQ flow that yields up to $20×$ maximum JJ reduction and an average of $4.3×$ on ISCAS85, EPFL, and ISCAS89 benchmarks, with favorable clock-tree characteristics compared to state-of-the-art. These results advance superconducting circuit design automation and offer a path toward higher logic density in non-latching emerging technologies.

Abstract

Gate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced alternating SFQ (xSFQ) logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80\% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites.

Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic

TL;DR

The paper tackles the challenge of clocked synthesis in superconducting SFQ circuits by introducing clock-free xSFQ logic with dual-rail alternating encoding, enabling complete design automation without clock distribution. It develops a complete xSFQ standard cell library (LA/FA at JJs, DROC storage with -JJ preloading, and characterization data) and links xSFQ to AIG/domino optimizations to aggressively reduce resource usage. The authors demonstrate a comprehensive RTL-to-xSFQ flow that yields up to maximum JJ reduction and an average of on ISCAS85, EPFL, and ISCAS89 benchmarks, with favorable clock-tree characteristics compared to state-of-the-art. These results advance superconducting circuit design automation and offer a path toward higher logic density in non-latching emerging technologies.

Abstract

Gate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced alternating SFQ (xSFQ) logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80\% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites.
Paper Structure (20 sections, 1 equation, 7 figures, 6 tables)

This paper contains 20 sections, 1 equation, 7 figures, 6 tables.

Table of Contents

  1. Introduction
  2. Standard Cell Library
  3. xSFQ logic gates
  4. xSFQ storage elements
  5. Library characterization
  6. Logic Synthesis & Optimization
  7. Circuits without synchronous elements
  8. Direct RTL-to-xSFQ mapping
  9. Splitters minimization
  10. LA-FA pairs minimization with AIG optimizations
  11. LA/FA cells minimization with polarity optimizations
  12. xSFQ like domino logic.
  13. Circuits with synchronous elements
  14. Evaluation
  15. Setup
  16. ...and 5 more sections

Figures (7)

  • Figure 1: An xSFQ logical cycle consists of two synchronous phases (clock cycles): excite and relax. The value of an alternating binary variable appears during the excite phase and is followed by its complement during the relax phase.
  • Figure 2: Schematics and SPICE waveforms for Last Arrival (Panel i) and First Arrival (Panel ii) cells.
  • Figure 3: Block diagram (Panel i) and SPICE waveform (Panel ii) for a DROC cell with DC-to-SFQ preloading hardware. Symbol $m$ denotes a merger. The highlighted part of the waveform shows how we externally set the DROC cell and its response to the arriving clock pulse.
  • Figure 4: Minimal AIG of a full adder (Panel i). AIG nodes represent AND operations, while dotted lines indicate inversions. Isomorphic xSFQ circuit (Panel ii). Subscripts $p$ and $n$ denote the positive and negative polarities, respectively, of each dual-rail signal.
  • Figure 5: Full adder circuits consisting of 11 (Panel i) and 10 (Panel ii) LA/FA cells following our polarity optimizations.
  • ...and 2 more figures