Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks

TL;DR

This paper tackles the challenge of deploying neural classifiers in printed electronics by focusing on the sensor-processor interface, ternary neural networks, and approximate computation to meet power and area constraints. It introduces a custom ABC to replace ADCs, enabling a multiplier-free TNN with fixed signed weights and XNOR-based outputs, and couples this with a three-phase evolutionary framework to approximate popcount and popcount-compare circuits. The result is an end-to-end, open-source digital printed classifier that achieves up to 32×–42× reductions in area and 19× reductions in power when including interface costs, while maintaining comparable accuracy on multiple sensor datasets. The approach demonstrates practical viability for energy-harvester-powered, on-sensor processing and offers scalable methodologies for hardware-friendly neural inference in printed electronics.

Abstract

Printed electronics offer ultra-low manufacturing costs and the potential for on-demand fabrication of flexible hardware. However, significant intrinsic constraints stemming from their large feature sizes and low integration density pose design challenges that hinder their practicality. In this work, we conduct a holistic exploration of printed neural network accelerators, starting from the analog-to-digital interface - a major area and power sink for sensor processing applications - and extending to networks of ternary neurons and their implementation. We propose bespoke ternary neural networks using approximate popcount and popcount-compare units, developed through a multi-phase evolutionary optimization approach and interfaced with sensors via customizable analog-to-binary converters. Our evaluation results show that the presented designs outperform the state of the art, achieving at least 6x improvement in area and 19x in power. To our knowledge, they represent the first open-source digital printed neural network classifiers capable of operating with existing printed energy harvesters.

Figures (8)

• Figure 1: Panel a: A $4$-bit flash ADC. Panel b: Proposed analog-to-binary converter. The ratio R$_1$/R$_2$ is used to regulate the voltage threshold at which an input feature becomes 1. $V_{in}$ denotes the voltage output of the sensor, which feeds the two converters (a) or (b).
• Figure 2: Bespoke $(3,2,2)$ TNN circuit with $[[[0,1,-1],[-1,-1,1]], [[1,-1],[1,1]] ]$ weights.
• Figure 3: Overview of the proposed three-phase TNN approximation framework, including Cartesian genetic programming for popcount circuit approximations in Phase 1, a Pareto analysis for identifying optimal combinations of popcount circuits for the construction of approximate popcount-compare circuits in Phase 2, and their integration into bespoke TNN circuits using the NSGA-II evolutionary algorithm in Phase 3. The underlying technology assumed is EGFET, operating at voltages as low as 0.6-1 V.
• Figure 4: Comparison between the proposed approximation approach and the previously used truncation technique for PCC circuits of various sizes. The results displayed are based on post-synthesis area measurements.
• Figure 5: Panel a: Trade-off illustration for three PCC circuits applied to the Arrhythmia dataset. The circuits are characterized by their sizes $\boldsymbol{(n_{pos}, n_{neg})}$: black $\boldsymbol{(45, 39)}$, purple $\boldsymbol{(47, 30)}$, and pink $\boldsymbol{(60, 29)}$. Panel b: Distribution of distance error for Pareto optimal PCC circuits of size $\boldsymbol{n_{pos}=45, n_{neg}=39}$ (corresponding to the black line in Panel a). Area results are post-synthesis and normalized relative to the exact circuit.