Automated Physical Design Watermarking Leveraging Graph Neural Networks
Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar
TL;DR
AutoMarks addresses IP protection for IC layouts by introducing a graph neural network–driven watermarking framework that automates the region search, watermark insertion, and extraction. By representing layouts as graphs with physical and semantic features, the method learns to predict fidelity loss from watermarking and selects watermark regions that preserve layout quality while enabling ownership verification. The approach demonstrates transferability to unseen designs and resilience against removal and forging attacks, with experimental evidence on ISPD'15 and ISPD'19 benchmarks showing reduced search time and 100% watermark extraction rate. This enables scalable, secure protection of physical design IP in contemporary IC design pipelines.
Abstract
This paper presents AutoMarks, an automated and transferable watermarking framework that leverages graph neural networks to reduce the watermark search overheads during the placement stage. AutoMarks's novel automated watermark search is accomplished by (i) constructing novel graph and node features with physical, semantic, and design constraint-aware representation; (ii) designing a data-efficient sampling strategy for watermarking fidelity label collection; and (iii) leveraging a graph neural network to learn the connectivity between cells and predict the watermarking fidelity on unseen layouts. Extensive evaluations on ISPD'15 and ISPD'19 benchmarks demonstrate that our proposed automated methodology: (i) is capable of finding quality-preserving watermarks in a short time; and (ii) is transferable across various designs, i.e., AutoMarks trained on one layout is generalizable to other benchmark circuits. AutoMarks is also resilient against potential watermark removal and forging attacks
