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Utilizing Generative Adversarial Networks for Image Data Augmentation and Classification of Semiconductor Wafer Dicing Induced Defects

Zhining Hu, Tobias Schlosser, Michael Friedrich, André Luiz Vieira e Silva, Frederik Beuth, Danny Kowerko

TL;DR

This paper tackles data scarcity and class imbalance in automated defect classification for semiconductor wafer dicing. It proposes GAN-based data augmentation using DCGAN, CycleGAN, and StyleGAN3 to synthesize realistic street defects and improve a ResNet152V2 classifier trained in PyTorch. The results show GAN-based hybrid augmentation can substantially boost balanced accuracy, with DCGAN achieving up to 88.2% BA and up to 23.1 percentage points improvement over a baseline. The work demonstrates a practical approach to improve yield optimization in production and outlines steps toward standardized image resolutions and hybrid augmentation strategies for broader defect classes.

Abstract

In semiconductor manufacturing, the wafer dicing process is central yet vulnerable to defects that significantly impair yield - the proportion of defect-free chips. Deep neural networks are the current state of the art in (semi-)automated visual inspection. However, they are notoriously known to require a particularly large amount of data for model training. To address these challenges, we explore the application of generative adversarial networks (GAN) for image data augmentation and classification of semiconductor wafer dicing induced defects to enhance the variety and balance of training data for visual inspection systems. With this approach, synthetic yet realistic images are generated that mimic real-world dicing defects. We employ three different GAN variants for high-resolution image synthesis: Deep Convolutional GAN (DCGAN), CycleGAN, and StyleGAN3. Our work-in-progress results demonstrate that improved classification accuracies can be obtained, showing an average improvement of up to 23.1 % from 65.1 % (baseline experiment) to 88.2 % (DCGAN experiment) in balanced accuracy, which may enable yield optimization in production.

Utilizing Generative Adversarial Networks for Image Data Augmentation and Classification of Semiconductor Wafer Dicing Induced Defects

TL;DR

This paper tackles data scarcity and class imbalance in automated defect classification for semiconductor wafer dicing. It proposes GAN-based data augmentation using DCGAN, CycleGAN, and StyleGAN3 to synthesize realistic street defects and improve a ResNet152V2 classifier trained in PyTorch. The results show GAN-based hybrid augmentation can substantially boost balanced accuracy, with DCGAN achieving up to 88.2% BA and up to 23.1 percentage points improvement over a baseline. The work demonstrates a practical approach to improve yield optimization in production and outlines steps toward standardized image resolutions and hybrid augmentation strategies for broader defect classes.

Abstract

In semiconductor manufacturing, the wafer dicing process is central yet vulnerable to defects that significantly impair yield - the proportion of defect-free chips. Deep neural networks are the current state of the art in (semi-)automated visual inspection. However, they are notoriously known to require a particularly large amount of data for model training. To address these challenges, we explore the application of generative adversarial networks (GAN) for image data augmentation and classification of semiconductor wafer dicing induced defects to enhance the variety and balance of training data for visual inspection systems. With this approach, synthetic yet realistic images are generated that mimic real-world dicing defects. We employ three different GAN variants for high-resolution image synthesis: Deep Convolutional GAN (DCGAN), CycleGAN, and StyleGAN3. Our work-in-progress results demonstrate that improved classification accuracies can be obtained, showing an average improvement of up to 23.1 % from 65.1 % (baseline experiment) to 88.2 % (DCGAN experiment) in balanced accuracy, which may enable yield optimization in production.
Paper Structure (11 sections, 2 figures, 5 tables)

This paper contains 11 sections, 2 figures, 5 tables.

Table of Contents

  1. Introduction and motivation
  2. Fundamentals and implementation
  3. Generative adversarial networks
  4. Designed system
  5. Test results, evaluation, and discussion
  6. Data sets and experimental configurations
  7. Results
  8. Impact of data balancing on model performance
  9. Comparative analysis of GAN architectures
  10. Effectiveness across different wafer types
  11. Conclusion and outlook

Figures (2)

  • Figure 1: Wafer overview with chips and dicing streets (reprinted and adapted from schlosser_novel_2019, copyright IEEE).
  • Figure 2: Designed visual fault synthesis and inspection system for dicing street generation and classification.