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SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning

Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija

TL;DR

The paper tackles the challenge of selecting appropriate STT-RAM cache retention times to balance latency and energy across diverse workloads. It introduces SCART, a KNN-based predictor that uses readily available SRAM performance-counter statistics to forecast the optimal STT-RAM retention time, enabling both design-time and runtime retention-time provisioning with reduced exploration overhead. Empirical results across SPEC CPU2006, MiBench, and GAP show SCART achieving average latency reductions of about 20.3% and energy reductions of about 29.1% over a homogeneous retention, while cutting exploration overhead by roughly 52.6% compared with exhaustive search. The approach demonstrates robustness in single- and multi-core scenarios and offers practical potential for runtime cache management in evolving STT-RAM architectures, with future work focusing on hardware integration and reducing labeling requirements.

Abstract

Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work.

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning

TL;DR

The paper tackles the challenge of selecting appropriate STT-RAM cache retention times to balance latency and energy across diverse workloads. It introduces SCART, a KNN-based predictor that uses readily available SRAM performance-counter statistics to forecast the optimal STT-RAM retention time, enabling both design-time and runtime retention-time provisioning with reduced exploration overhead. Empirical results across SPEC CPU2006, MiBench, and GAP show SCART achieving average latency reductions of about 20.3% and energy reductions of about 29.1% over a homogeneous retention, while cutting exploration overhead by roughly 52.6% compared with exhaustive search. The approach demonstrates robustness in single- and multi-core scenarios and offers practical potential for runtime cache management in evolving STT-RAM architectures, with future work focusing on hardware integration and reducing labeling requirements.

Abstract

Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work.
Paper Structure (15 sections, 5 figures, 3 tables)

This paper contains 15 sections, 5 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Multi-retention and Hybrid STT-RAM Caches
  4. Cross-Architectural Prediction
  5. STT-RAM Cache Retention Time Prediction (SCART)
  6. SCART Model Architecture
  7. Machine Learning Classifier Comparison and Selection
  8. KNN Classifier Tuning
  9. Experimental Setup
  10. results
  11. Comparison to the Base Retention Time
  12. Comparison to Exhaustive Search
  13. SCART Execution in a Multi-Programmed Scenario
  14. Comparison to Prior Work and Implementation Overhead
  15. Conclusion and Future Work

Figures (5)

  • Figure 1: High-level overview of predictive model
  • Figure 2: Selection of optimal number of features for latency and energy optimization. Tuning began with 59 features, and features were iteratively removed to maximize F-score and minimize prediction time.
  • Figure 3: Percentage latency and energy improvements using SCART model compared to the base retention time of 1ms.
  • Figure 4: SCART vs exhaustive search latency and energy improvements compared to the base (1$m$s) retention time. Geometric means of the results are presented.
  • Figure 5: SCART latency and energy savings in a multi-programmed scenario