Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

TL;DR

The paper addresses the challenge of integrating quantum accelerators into HPC environments to unlock practical quantum advantages. It proposes a Unified Quantum Platform (UQP) comprising a runtime library, a cross-technology instruction set architecture (ISA), and a quantum control processor (QCP) to unify software and hardware interfaces across superconducting and neutral-atom technologies. Key contributions include a unified runtime that maps Quantum Intermediate Representation (QIR) to a novel hybrid ISA, a technology-agnostic QCP microarchitecture, and extended quantum instructions for neutral-atom systems, with demonstration of correctness and scalability showing super-linear resource growth with qubit count. Workflow verification demonstrates binary portability across quantum modalities, and performance analysis indicates the approach can scale to larger quantum systems while providing predictable resource planning. Collectively, the work provides a foundational cross-technology HPCQC platform that could enable more practical and scalable quantum acceleration in high-performance computing settings.

Abstract

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale super-linearly with number of qubits, which is critical to support scalability efforts in QC hardware.

Figures (8)

• Figure 1: Abstract representation of a full-stack quantum computer.
• Figure 2: Integration Scenarios. (a) Loose Integration -- Standalone, (b) Loose Integration -- Co-located, (c) Tight Integration -- Co-located and (d) Tight Integration -- On-node.
• Figure 3: Abstract HPCQC workflow. The figure shows five components: login node, HPC management node, HPC compute node, HPCQC management node and HPCQC compute node.
• Figure 4: The expected progress of cross-technology execution within an system.
• Figure 5: System architecture of the proposed cross-technology quantum control processor.