Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits

Yanyue Xie, Peiyan Dong, Geng Yuan, Zhengang Li, Masoud Zabihi, Chao Wu, Sung-En Chang, Xufeng Zhang, Xue Lin, Caiwen Ding, Nobuyuki Yoshikawa, Olivia Chen, Yanzhi Wang

TL;DR

SuperFlow delivers a fully-customized RTL-to-GDS design flow tailored for AQFP superconducting circuits, addressing the unique clocking, spacing, and fan-out constraints throughout logic synthesis, placement, routing, and layout generation. By converting CMOS AOI nets to MAJ-based AQFP nets, inserting buffers/splitters, and employing a layer-wise A* routing with space expansion, the flow achieves timing-aware, constraint-compliant designs. Experimental results show 12.8% average wirelength reduction and 12.1% timing improvement over state-of-the-art AQFP placers, with substantial reductions in buffers for large circuits. This integrated approach enables more aggressive optimization and paves the way for practical AQFP implementations in domains like RISC-V CPUs and neural-network accelerators.

Abstract

Superconducting circuits, like Adiabatic Quantum-Flux-Parametron (AQFP), offer exceptional energy efficiency but face challenges in physical design due to sophisticated spacing and timing constraints. Current design tools often neglect the importance of constraint adherence throughout the entire design flow. In this paper, we propose SuperFlow, a fully-customized RTL-to-GDS design flow tailored for AQFP devices. SuperFlow leverages a synthesis tool based on CMOS technology to transform any input RTL netlist to an AQFP-based netlist. Subsequently, we devise a novel place-and-route procedure that simultaneously considers wirelength, timing, and routability for AQFP circuits. The process culminates in the generation of the AQFP circuit layout, followed by a Design Rule Check (DRC) to identify and rectify any layout violations. Our experimental results demonstrate that SuperFlow achieves 12.8% wirelength improvement on average and 12.1% better timing quality compared with previous state-of-the-art placers for AQFP circuits.

SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits

TL;DR

SuperFlow delivers a fully-customized RTL-to-GDS design flow tailored for AQFP superconducting circuits, addressing the unique clocking, spacing, and fan-out constraints throughout logic synthesis, placement, routing, and layout generation. By converting CMOS AOI nets to MAJ-based AQFP nets, inserting buffers/splitters, and employing a layer-wise A* routing with space expansion, the flow achieves timing-aware, constraint-compliant designs. Experimental results show 12.8% average wirelength reduction and 12.1% timing improvement over state-of-the-art AQFP placers, with substantial reductions in buffers for large circuits. This integrated approach enables more aggressive optimization and paves the way for practical AQFP implementations in domains like RISC-V CPUs and neural-network accelerators.

Abstract

Superconducting circuits, like Adiabatic Quantum-Flux-Parametron (AQFP), offer exceptional energy efficiency but face challenges in physical design due to sophisticated spacing and timing constraints. Current design tools often neglect the importance of constraint adherence throughout the entire design flow. In this paper, we propose SuperFlow, a fully-customized RTL-to-GDS design flow tailored for AQFP devices. SuperFlow leverages a synthesis tool based on CMOS technology to transform any input RTL netlist to an AQFP-based netlist. Subsequently, we devise a novel place-and-route procedure that simultaneously considers wirelength, timing, and routability for AQFP circuits. The process culminates in the generation of the AQFP circuit layout, followed by a Design Rule Check (DRC) to identify and rectify any layout violations. Our experimental results demonstrate that SuperFlow achieves 12.8% wirelength improvement on average and 12.1% better timing quality compared with previous state-of-the-art placers for AQFP circuits.
Paper Structure (22 sections, 3 equations, 5 figures, 4 tables, 1 algorithm)

This paper contains 22 sections, 3 equations, 5 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background
  3. AQFP Superconducting Logic
  4. AQFP Clocking Architecture
  5. Challenges of AQFP Physical Design
  6. Methods
  7. Overall AQFP Design Flow
  8. Majority-Based Logic Synthesis for AQFP
  9. Majority Netlist Conversion
  10. Buffer and Splitter Insertion
  11. AQFP Placement
  12. Problem Formulation
  13. Global Placement
  14. Detailed Placement
  15. Layer-Wise Fast A* Routing with Space Expansion
  16. ...and 7 more sections

Figures (5)

  • Figure 1: The symbols of AQFP logic gates. (a) and gate; (b) nand gate; (c) majority gate; (d) splitter gate.
  • Figure 2: AQFP clocking architecture. AQFP clocking scheme utilizes one DC and two AC signals to create a four-phase clocking scheme. The two AC signals have a phase difference of 90 degrees. The intricate zigzag clocking signals impose strict timing constraints on AQFP logic cells and formulate a deep-pipelined architecture.
  • Figure 3: The overall design flow of SuperFlow.
  • Figure 4: An illustration of the detailed placement stage where one clock phase has the widest width and all cells are abutted. (a) When cell candidates are strictly matched to cells of identical sizes, it is possible to end up with a sub-optimal state, leaving some nets with timing violations (highlighted by the red line, SPL3 in phase i to MAJ3 in phase i+1); (b) By allowing flexibility in cell candidates and permitting cell swaps to avoid overlaps (MAJ3, AND, and BUF in phase i-1, in contrast to only MAJ3 and AND in (a)), the detailed placement result is better than (a), exhibiting no timing violations.
  • Figure 5: Layout for AQFP circuits apc128.