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MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning

Mingju Liu, Daniel Robinson, Yingjie Li, Cunxi Yu

TL;DR

The paper tackles the large design-space challenge of technology mapping by proposing MapTune, a reinforcement-learning–guided framework that selectively samples a subset of cells from a technology library during mapping. By formulating the problem with a multi-armed bandit and Q-learning variants and integrating with the ABC flow, MapTune seeks to minimize the Area-Delay Product ($ADP$) through design-specific library tuning. Extensive experiments across five benchmark suites and four libraries show MapTune achieving about $ADP$ improvements of roughly 22.5%, with notable Pareto-frontier gains that trade off delay and area favorably. The work demonstrates that carefully tuned, partially sampled libraries can outperform full-library mappings, enabling faster design space exploration with practical QoR benefits, and it is released as an open-source tool.

Abstract

Technology mapping involves mapping logical circuits to a library of cells. Traditionally, the full technology library is used, leading to a large search space and potential overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune framework that addresses this challenge by utilizing reinforcement learning to make design-specific choices during cell selection. By learning from the environment, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries and technology mappers. The experimental results demonstrate that MapTune achieves higher mapping accuracy and reducing delay/area across diverse circuit designs, technology libraries and mappers. The paper also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area trade-off. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0 and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 22.54\% among all different exploration settings in MapTune. The improvements are consistently remained for four different technologies (7nm, 45nm, 130nm, and 180 nm) and two different mappers.

MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning

TL;DR

The paper tackles the large design-space challenge of technology mapping by proposing MapTune, a reinforcement-learning–guided framework that selectively samples a subset of cells from a technology library during mapping. By formulating the problem with a multi-armed bandit and Q-learning variants and integrating with the ABC flow, MapTune seeks to minimize the Area-Delay Product () through design-specific library tuning. Extensive experiments across five benchmark suites and four libraries show MapTune achieving about improvements of roughly 22.5%, with notable Pareto-frontier gains that trade off delay and area favorably. The work demonstrates that carefully tuned, partially sampled libraries can outperform full-library mappings, enabling faster design space exploration with practical QoR benefits, and it is released as an open-source tool.

Abstract

Technology mapping involves mapping logical circuits to a library of cells. Traditionally, the full technology library is used, leading to a large search space and potential overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune framework that addresses this challenge by utilizing reinforcement learning to make design-specific choices during cell selection. By learning from the environment, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries and technology mappers. The experimental results demonstrate that MapTune achieves higher mapping accuracy and reducing delay/area across diverse circuit designs, technology libraries and mappers. The paper also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area trade-off. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0 and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 22.54\% among all different exploration settings in MapTune. The improvements are consistently remained for four different technologies (7nm, 45nm, 130nm, and 180 nm) and two different mappers.
Paper Structure (14 sections, 6 equations, 4 figures, 3 tables)

This paper contains 14 sections, 6 equations, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Technology Mapping and Library
  4. Learning-based techniques in EDA
  5. MapTune Case Studies
  6. Approach
  7. Formulation of MapTune
  8. Implementation
  9. MapTune-MAB
  10. MapTune-Q
  11. Results
  12. Technology Mapping Results
  13. Pareto-Optimal Exploration
  14. Conclusions

Figures (4)

  • Figure 1: Technology mapping results of selected designs: Baseline: All 161 cells of ASAP7 library; Sampling 1: Randomly sampling 75 - 100 cells; Sampling 2: Randomly sampling 100 - 125 cells; Sampling 3: Randomly sampling 125 - 150 cells.
  • Figure 2: MapTune Framework Overview. Termination is based on the user-defined number of iterations for $p$ update.
  • Figure 3: Comparison of ADP convergence rates of nine selected designs mapped on ASAP7 library tuned by various MapTune-MAB and MapTune-Q methods with ABC Delay-driven mapper. Baselines (constant one) are collected with the original technology library. *The lower the better.
  • Figure 4: Comparison of final converged ADP of eight selected designs mapped on various technology libraries tuned by MapTune-MAB and MapTune-Q methods with ABC Delay-driven (D) and Area-driven (A) mappers. Baselines (constant one) are collected with the original technology library. *The lower the better.