Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Accurate Mapping of RNNs on Neuromorphic Hardware with Adaptive Spiking Neurons

Gauthier Boeshertz, Giacomo Indiveri, Manu Nair, Alpha Renner

TL;DR

The paper tackles the challenge of converting rate-based RNNs to spike-based neuromorphic hardware by introducing a $\Sigma\Delta$-spiking neuron and a low-pass RNN ($lpRNN$) that jointly encode signals via spike timing and low-pass dynamics. The method trains an ANN with 3-bit weights and maps it to Loihi, using time-constant alignment $\tau_{SNN}=T_{ANN}/T_{SNN}$ and weight scaling to fit hardware constraints, achieving state-of-the-art on-chip speech classification on the Heidelberg Digits and Google Speech Commands datasets. The results underscore the importance of synaptic adaptation and spike-timing encoding for robust RNN→SNN conversion and demonstrate the practicality of ultra-low-power edge inference with modest-precision weights. The findings suggest broad applicability of the $\Sigma\Delta$-mechanism for low-power, real-time processing in audio and biomedical domains, along with future work on learning delays and time constants to extend time-scale flexibility.

Abstract

Thanks to their parallel and sparse activity features, recurrent neural networks (RNNs) are well-suited for hardware implementation in low-power neuromorphic hardware. However, mapping rate-based RNNs to hardware-compatible spiking neural networks (SNNs) remains challenging. Here, we present a $ΣΔ$-low-pass RNN (lpRNN): an RNN architecture employing an adaptive spiking neuron model that encodes signals using $ΣΔ$-modulation and enables precise mapping. The $ΣΔ$-neuron communicates analog values using spike timing, and the dynamics of the lpRNN are set to match typical timescales for processing natural signals, such as speech. Our approach integrates rate and temporal coding, offering a robust solution for the efficient and accurate conversion of RNNs to SNNs. We demonstrate the implementation of the lpRNN on Intel's neuromorphic research chip Loihi, achieving state-of-the-art classification results on audio benchmarks using 3-bit weights. These results call for a deeper investigation of recurrency and adaptation in event-based systems, which may lead to insights for edge computing applications where power-efficient real-time inference is required.

Accurate Mapping of RNNs on Neuromorphic Hardware with Adaptive Spiking Neurons

TL;DR

The paper tackles the challenge of converting rate-based RNNs to spike-based neuromorphic hardware by introducing a -spiking neuron and a low-pass RNN () that jointly encode signals via spike timing and low-pass dynamics. The method trains an ANN with 3-bit weights and maps it to Loihi, using time-constant alignment and weight scaling to fit hardware constraints, achieving state-of-the-art on-chip speech classification on the Heidelberg Digits and Google Speech Commands datasets. The results underscore the importance of synaptic adaptation and spike-timing encoding for robust RNN→SNN conversion and demonstrate the practicality of ultra-low-power edge inference with modest-precision weights. The findings suggest broad applicability of the -mechanism for low-power, real-time processing in audio and biomedical domains, along with future work on learning delays and time constants to extend time-scale flexibility.

Abstract

Thanks to their parallel and sparse activity features, recurrent neural networks (RNNs) are well-suited for hardware implementation in low-power neuromorphic hardware. However, mapping rate-based RNNs to hardware-compatible spiking neural networks (SNNs) remains challenging. Here, we present a -low-pass RNN (lpRNN): an RNN architecture employing an adaptive spiking neuron model that encodes signals using -modulation and enables precise mapping. The -neuron communicates analog values using spike timing, and the dynamics of the lpRNN are set to match typical timescales for processing natural signals, such as speech. Our approach integrates rate and temporal coding, offering a robust solution for the efficient and accurate conversion of RNNs to SNNs. We demonstrate the implementation of the lpRNN on Intel's neuromorphic research chip Loihi, achieving state-of-the-art classification results on audio benchmarks using 3-bit weights. These results call for a deeper investigation of recurrency and adaptation in event-based systems, which may lead to insights for edge computing applications where power-efficient real-time inference is required.
Paper Structure (7 sections, 3 equations, 3 figures, 2 tables)

This paper contains 7 sections, 3 equations, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Model
  3. The $\Sigma\Delta$-spiking neuron model
  4. The low-pass RNN model
  5. Results
  6. Discussion
  7. Methods

Figures (3)

  • Figure 1: \ref{['fig:sd_blockdiag']}. Block diagram of a $\Sigma\Delta$-neuron. \ref{['fig:sd_trans']}. Evolution of the feedback signal $s(t)$ following the the input. Whenever it decays too far below the input, the neuron generates a spike ($y(t)$) which increases the feedback current. Panels from nair2019mapping.
  • Figure 2: Architecture of the lpRNN network.
  • Figure 3: Multi-compartment $\Sigma\Delta$-neuron on Loihi