Profiling quantum circuits for their efficient execution on single- and multi-core architectures

TL;DR

To address scalability on NISQ and modular quantum devices, the paper develops a comprehensive circuit profiling framework that uses graph-theoretic metrics from the qubit interaction graph (IG) and gate-dependency graph (GDG), plus circuit density and repetitive-subcircuit features. It then correlates these features with quantum circuit mapping performance across multiple mappers and hardware configurations, using a two-stage clustering to form circuit families. The study finds that structure-derived parameters, not just size, largely govern mapping efficiency and inter-core communication, with parameter importance depending on device topology and mapper. These insights enable application-aware co-design of quantum compilers and hardware and pave the way for representative benchmarks and scalable modular quantum architectures.

Abstract

Application-specific quantum computers offer the most efficient means to tackle problems intractable by classical computers. Realizing these architectures necessitates a deep understanding of quantum circuit properties and their relationship to execution outcomes on quantum devices. Our study aims to perform for the first time a rigorous examination of quantum circuits by introducing graph theory-based metrics extracted from their qubit interaction graph and gate dependency graph alongside conventional parameters describing the circuit itself. This methodology facilitates a comprehensive analysis and clustering of quantum circuits. Furthermore, it uncovers a connection between parameters rooted in both qubit interaction and gate dependency graphs, and the performance metrics for quantum circuit mapping, across a range of established quantum device and mapping configurations. Among the various device configurations, we particularly emphasize modular (i.e., multi-core) quantum computing architectures due to their high potential as a viable solution for quantum device scalability. This thorough analysis will help us to: i) identify key attributes of quantum circuits that affect the quantum circuit mapping performance metrics; ii) predict the performance on a specific chip for similar circuit structures; iii) determine preferable combinations of mapping techniques and hardware setups for specific circuits; and iv) define representative benchmark sets by clustering similarly structured circuits.

Figures (12)

• Figure 1: Initial mapping of a quantum circuit (middle) to a single-core (left) or multi-core device (right); For the latter case, the quantum circuit is partitioned into two highly connected circuit slices so that any communication between the two cores is minimized.
• Figure 2: An exemplary quantum circuit (a) and its corresponding qubit interaction graph (b) and gate dependency graph (c).
• Figure 3: Topologies of the quantum architectures used in our experiments: a) Surface-17; b) IBM Rochester; c) Rigetti 16-q Aspen and d) Google Bristlecone. Figures and device configurations taken from: lao2021timingIBMRigettiGoodrich2018PracticalGB.
• Figure 3: K-Means settings: Single-core architecture
• Figure 4: In our experiments, we examined two distinct multi-core architectures: a) All-to-all connected cores and b) 2D Grid core connectivity. Each node in the two graphs on the left represents a core, while the edges correspond to communication links between the cores. On the right, the intra-core qubit topology is displayed, comprising 10 all-to-all connected qubits. We chose these topologies due to their ability to offer a simplified representation of architectures anticipated to emerge in the near future. This approach enables us to promptly address the immediate need for mapping solutions based on minimizing inter-core communication before going into more complex architectures bandic2023mappingqubo.