Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation

TL;DR

Graphitron introduces a domain-specific language for agile FPGA-based graph accelerator generation, enabling high-level expression of vertex-centric and edge-centric graph processing while delegating hardware optimization to a compiler back-end. The three-stage Graphitron compiler (front-end, middle-end, back-end) translates graph tasks into OpenCL kernels, automatically applying pipelining, data shuffling, and memory-caching optimizations to produce versatile accelerators. Empirical results show BFS on Graphitron matches or surpasses a state-of-the-art template-based framework and delivers substantial speedups for PPR and CGAW, with notable gains from memory-access optimizations. Overall, Graphitron enhances accelerator design productivity and flexibility without sacrificing competitive performance, opening avenues for broader algorithm coverage and rapid hardware generation on FPGA platforms.

Abstract

FPGA-based graph processing accelerators, enabling extensive customization, have demonstrated significant energy efficiency over general computing engines like CPUs and GPUs. Nonetheless, customizing accelerators to diverse graph processing algorithms with distinct computational patterns remains challenging and error-prone for high-level application users. To this end, template-based approaches have been developed to automate the graph processing accelerator generation. Although these frameworks significantly enhance the design productivity, the templates often result in closely coupled algorithms, programming models, and architectures, severely limiting the versatility of the targeted graph processing algorithms and their applicability to high-level users. Furthermore, the limitations of the frameworks are usually ambiguous due to the absence of a rigorous grammar definition. To overcome these challenges, we introduce Graphitron, a domain-specific language (DSL), which allows users to generate customized accelerators for a wide range of graph processing algorithms on FPGAs without engaging with the complexities of low-level FPGA designs. Graphitron, by defining vertices and edges as primitive data types, naturally facilitates the description of graph algorithms using edge-centric or vertex-centric programming models. The Graphitron back-end employs a suite of hardware optimization techniques including pipelining, data shuffling, and memory access optimization that are independent with the specific algorithms, supporting the creation of versatile graph processing accelerators. Our experiments indicate that accelerators crafted using Graphitron achieve comparable performance to that generated with template-based design framework. Moreover, it exhibits exceptional flexibility in algorithm expression and significantly enhance accelerator design productivity.

Figures (10)

• Figure 1: Top-down BFS with ECP programming model
• Figure 2: Direction based BFS with VCP programming model
• Figure 3: Overview of Graphitron Compiler.
• Figure 4: Back-end Framework
• Figure 5: The original sssp function