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SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions

Jitendra Bhandari, Rajat Sadhukhan, Prashanth Krishnamurthy, Farshad Khorrami, Ramesh Karri

TL;DR

This work addresses supply-chain hardware security risks by enabling rapid RTL-level hardware Trojan assessment without offline training. It introduces SENTAUR, a conversational LLM-driven workflow that generates synthesizable HTs from design specifications, sanitizes them to ensure post-synthesis persistence, and validates them on real hardware. The framework is demonstrated using Trust-Hub benchmarks and a Xilinx FPGA, showing a diverse taxonomy of triggers and payloads and enabling both attack-space exploration and countermeasure development. By automating RTL modifications and analysis, SENTAUR offers a practical tool for designers and defenders to rapidly evaluate HT threats and strengthen security in outsourcing contexts.

Abstract

A globally distributed IC supply chain brings risks due to untrusted third parties. The risks span inadvertent use of hardware Trojan (HT), inserted Intellectual Property (3P-IP) or Electronic Design Automation (EDA) flows. HT can introduce stealthy HT behavior, prevent an IC work as intended, or leak sensitive data via side channels. To counter HTs, rapidly examining HT scenarios is a key requirement. While Trust-Hub benchmarks are a good starting point to assess defenses, they encompass a small subset of manually created HTs within the expanse of HT designs. Further, the HTs may disappear during synthesis. We propose a large language model (LLM) framework SENTAUR to generate a suite of legitimate HTs for a Register Transfer Level (RTL) design by learning its specifications, descriptions, and natural language descriptions of HT effects. Existing tools and benchmarks are limited; they need a learning period to construct an ML model to mimic the threat model and are difficult to reproduce. SENTAUR can swiftly produce HT instances by leveraging LLMs without any learning period and sanitizing the HTs facilitating their rapid assessment. Evaluation of SENTAUR involved generating effective, synthesizable, and practical HTs from TrustHub and elsewhere, investigating impacts of payloads/triggers at the RTL. While our evaluation focused on HT insertion, SENTAUR can generalize to automatically transform an RTL code to have defined functional modifications.

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions

TL;DR

This work addresses supply-chain hardware security risks by enabling rapid RTL-level hardware Trojan assessment without offline training. It introduces SENTAUR, a conversational LLM-driven workflow that generates synthesizable HTs from design specifications, sanitizes them to ensure post-synthesis persistence, and validates them on real hardware. The framework is demonstrated using Trust-Hub benchmarks and a Xilinx FPGA, showing a diverse taxonomy of triggers and payloads and enabling both attack-space exploration and countermeasure development. By automating RTL modifications and analysis, SENTAUR offers a practical tool for designers and defenders to rapidly evaluate HT threats and strengthen security in outsourcing contexts.

Abstract

A globally distributed IC supply chain brings risks due to untrusted third parties. The risks span inadvertent use of hardware Trojan (HT), inserted Intellectual Property (3P-IP) or Electronic Design Automation (EDA) flows. HT can introduce stealthy HT behavior, prevent an IC work as intended, or leak sensitive data via side channels. To counter HTs, rapidly examining HT scenarios is a key requirement. While Trust-Hub benchmarks are a good starting point to assess defenses, they encompass a small subset of manually created HTs within the expanse of HT designs. Further, the HTs may disappear during synthesis. We propose a large language model (LLM) framework SENTAUR to generate a suite of legitimate HTs for a Register Transfer Level (RTL) design by learning its specifications, descriptions, and natural language descriptions of HT effects. Existing tools and benchmarks are limited; they need a learning period to construct an ML model to mimic the threat model and are difficult to reproduce. SENTAUR can swiftly produce HT instances by leveraging LLMs without any learning period and sanitizing the HTs facilitating their rapid assessment. Evaluation of SENTAUR involved generating effective, synthesizable, and practical HTs from TrustHub and elsewhere, investigating impacts of payloads/triggers at the RTL. While our evaluation focused on HT insertion, SENTAUR can generalize to automatically transform an RTL code to have defined functional modifications.
Paper Structure (15 sections, 7 figures, 2 tables)

This paper contains 15 sections, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Key Contributions
  3. Related Works
  4. SENTAUR: Tool Flow and Capabilities
  5. Hardware Trojan Threat Model
  6. Motivating Use Case
  7. Tool Flow
  8. SENTAUR Tool Capabilities
  9. Signal Declarations and Connections
  10. File Manipulation
  11. Experimental Results
  12. Setup
  13. Result I: Analysis on Generation of HTs
  14. Result II: Assessment of HTs
  15. Conclusion and Discussion

Figures (7)

  • Figure 1: SENTAUR Flow and its scope in IC Supply Chain.
  • Figure 2: Post-synthesis Simulations of AES-T800
  • Figure 3: Schematic of Dual-port RAM by Xilinx without HT.
  • Figure 4: Dual-port RAM with HT inserted (State-based) by SENTAUR.
  • Figure 5: Expected outputs with and without presence (Performance degradation by introducing deadband) when the trigger condition is met.
  • ...and 2 more figures