Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity

TL;DR

The paper targets energy efficiency for FPGA-based DL accelerators in IoT by minimizing the expensive FPGA configuration phase during duty-cycle operation with periodic requests. It proposes a configuration-parameter tuning approach that achieves a $40.13\times$ reduction in per-workload-configuration energy and introduces Idle-Waiting to replace repeated reconfigurations for short $T_\text{req}$. An analytical model and hardware+simulation validation quantify executable workload items and system lifetime under a fixed energy budget, with idle-power-saving methods further boosting performance. Empirically, at a request period of $T_\text{req}=40$ ms within $E_{\text{Budget}}=4147\ \text{J}$, Idle-Waiting yields about $12.39\times$ longer lifetime and up to $2.23\times$ more workload items, and expands the practical duty-cycle range to $499.06$ ms, promising substantially longer sustainable IoT deployments.

Abstract

In the rapidly evolving Internet of Things (IoT) domain, we concentrate on enhancing energy efficiency in Deep Learning accelerators on FPGA-based heterogeneous platforms, aligning with the principles of sustainable computing. Instead of focusing on the inference phase, we introduce innovative optimizations to minimize the overhead of the FPGA configuration phase. By fine-tuning configuration parameters correctly, we achieved a 40.13-fold reduction in configuration energy. Moreover, augmented with power-saving methods, our Idle-Waiting strategy outperformed the traditional On-Off strategy in duty-cycle mode for request periods up to 499.06 ms. Specifically, at a 40 ms request period within a 4147 J energy budget, this strategy extends the system lifetime to approximately 12.39x that of the On-Off strategy. Empirically validated through hardware measurements and simulations, these optimizations provide valuable insights and practical methods for achieving energy-efficient and sustainable deployments in IoT.

Figures (11)

• Figure 1: Workloads in Duty-Cycle Mode
• Figure 2: Energy of a Workload Item
• Figure 3: Architecture for the Hardware designed for DL Accelerator
• Figure 4: Breakdown of FPGA Configuration Phase
• Figure 5: Illustration of On-Off strategy