MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs
Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
TL;DR
This work tackles the challenge of secure hardware design against power side-channel attacks (PSCAs) in the presence of glitches by showing that conventional high-level synthesis (HLS) can undermine masking guarantees. It introduces MaskedHLS, a domain-specific HLS flow that translates masked software into PSCA-secure hardware while automatically inserting and balancing registers at gadget-defined locations using retiming-based techniques. The approach yields RTL designs with substantially fewer registers (average ~73.9% reduction) and lower latency (average ~45.7% reduction) across PRESENT and AES S-box gadgets, and PSCA security is validated via TVLA analyses. These results demonstrate that gadget-aware register placement and path balancing are practical and effective for scalable, PSCA-secure hardware synthesis, with potential for further optimization in randomness handling.
Abstract
The design and synthesis of masked cryptographic hardware implementations that are secure against power side-channel attacks (PSCAs) in the presence of glitches is a challenging task. High-Level Synthesis (HLS) is a promising technique for generating masked hardware directly from masked software, offering opportunities for design space exploration. However, conventional HLS tools make modifications that alter the guarantee against PSCA security via masking, resulting in an insecure RTL. Moreover, existing HLS tools can't place registers at designated places and balance parallel paths in a cryptographic design which is needed to stop glitch propagation. This paper introduces a domain-specific HLS approach tailored to obtain a PSCA secure masked hardware implementation directly from a masked software implementation. It places the registers at specific locations required by the glitch-robust masking gadgets, resulting in a secure RTL. Moreover, our tool automatically balances parallel paths and facilitates a reduction in latency while preserving the PSCA security guaranteed by masking. Experimental results with the PRESENT Cipher's S-box and AES Canright's S-box masked with four state-of-the-art gadgets, show that MaskedHLS produces RTLs with 73.9% decrease in registers and 45.7% decrease in latency on an average} compared to manual register insertions. The PSCA security of the MaskedHLS generated RTLs is also shown with TVLA test.