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DeepGate3: Towards Scalable Circuit Representation Learning

Zhengyuan Shi, Ziyang Zheng, Sadaf Khan, Jianyuan Zhong, Min Li, Qiang Xu

TL;DR

GNN-based circuit representation learning faces scalability and generalization challenges on large netlists. DeepGate3 addresses these issues by fusing a DeepGate2 GNN backbone with two Transformer modules (Refine Transformer and Pooling Transformer), a workload-aware tokenization strategy, and a multi-task pre-training regime, complemented by a window-shifting fine-tuning approach for large AIGs. The work introduces a subgraph pooling mechanism, explicit attention masking via fanin/fanout cones, and ten cross-level losses that tie gate- and graph-level representations, achieving superior scalability and generalization, including enhanced performance in SAT solving. Together, these contributions deliver robust, scalable circuit representations applicable to large-scale EDA tasks and challenging downstream reasoning.

Abstract

Circuit representation learning has shown promising results in advancing the field of Electronic Design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology.

DeepGate3: Towards Scalable Circuit Representation Learning

TL;DR

GNN-based circuit representation learning faces scalability and generalization challenges on large netlists. DeepGate3 addresses these issues by fusing a DeepGate2 GNN backbone with two Transformer modules (Refine Transformer and Pooling Transformer), a workload-aware tokenization strategy, and a multi-task pre-training regime, complemented by a window-shifting fine-tuning approach for large AIGs. The work introduces a subgraph pooling mechanism, explicit attention masking via fanin/fanout cones, and ten cross-level losses that tie gate- and graph-level representations, achieving superior scalability and generalization, including enhanced performance in SAT solving. Together, these contributions deliver robust, scalable circuit representations applicable to large-scale EDA tasks and challenging downstream reasoning.

Abstract

Circuit representation learning has shown promising results in advancing the field of Electronic Design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology.
Paper Structure (19 sections, 13 equations, 7 figures, 4 tables, 1 algorithm)

This paper contains 19 sections, 13 equations, 7 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Related Work
  3. Circuit Representation Learning
  4. Transformer-Based Graph Learning
  5. Methodology
  6. Overview of DeepGate3
  7. DeepGate2 as Tokenzier
  8. Refine Transformer
  9. Pooling Transformer
  10. Model Pre-training
  11. Fine-tuning on Large AIGs
  12. Experiments
  13. Data Preparation
  14. Implementation Details
  15. Evaluation Metric
  16. ...and 4 more sections

Figures (7)

  • Figure 1: The overview of previous DeepGate2 shi2023deepgate2
  • Figure 2: The overview of DeepGate3
  • Figure 3: The example of fanin-fanout cones and the corresponding mask
  • Figure 4: The overview of functional pooling Transformer
  • Figure 5: The partitioned area of large AIG
  • ...and 2 more figures