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CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis

Prashanth Vijayaraghavan, Luyao Shi, Ehsan Degan, Xin Zhang

TL;DR

Circuit topology synthesis is challenging due to the enormous design space and limitations of traditional methods. The authors propose CIRCUITSYNTH, a two-phase LLM-based framework that first autoregressively generates circuit topologies from a component pool and then refines them using a circuit validity classifier and a differentiable generation objective with Gumbel-softmax. Key contributions include a large labeled dataset of valid/invalid topologies, a RoBERTa-based validity classifier, and a joint loss that improves validity and efficiency of generated circuits, as validated against SPICE simulations. The results show CircuitSynth outperforms zero-shot, ICL, and vanilla fine-tuning baselines, with smaller models achieving performance competitive with larger prompt-tuned models, highlighting its practical potential for automated power-converter design and design constraint adherence.

Abstract

Circuit topology generation plays a crucial role in the design of electronic circuits, influencing the fundamental functionality of the circuit. In this paper, we introduce CIRCUITSYNTH, a novel approach that harnesses LLMs to facilitate the automated synthesis of valid circuit topologies. With a dataset comprising both valid and invalid circuit configurations, CIRCUITSYNTH employs a sophisticated two-phase methodology, comprising Circuit Topology Generation and Circuit Topology Refinement. Experimental results demonstrate the effectiveness of CIRCUITSYNTH compared to various fine-tuned LLM variants. Our approach lays the foundation for future research aimed at enhancing circuit efficiency and specifying output voltage, thus enabling the automated generation of circuit topologies with improved performance and adherence to design requirements.

CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis

TL;DR

Circuit topology synthesis is challenging due to the enormous design space and limitations of traditional methods. The authors propose CIRCUITSYNTH, a two-phase LLM-based framework that first autoregressively generates circuit topologies from a component pool and then refines them using a circuit validity classifier and a differentiable generation objective with Gumbel-softmax. Key contributions include a large labeled dataset of valid/invalid topologies, a RoBERTa-based validity classifier, and a joint loss that improves validity and efficiency of generated circuits, as validated against SPICE simulations. The results show CircuitSynth outperforms zero-shot, ICL, and vanilla fine-tuning baselines, with smaller models achieving performance competitive with larger prompt-tuned models, highlighting its practical potential for automated power-converter design and design constraint adherence.

Abstract

Circuit topology generation plays a crucial role in the design of electronic circuits, influencing the fundamental functionality of the circuit. In this paper, we introduce CIRCUITSYNTH, a novel approach that harnesses LLMs to facilitate the automated synthesis of valid circuit topologies. With a dataset comprising both valid and invalid circuit configurations, CIRCUITSYNTH employs a sophisticated two-phase methodology, comprising Circuit Topology Generation and Circuit Topology Refinement. Experimental results demonstrate the effectiveness of CIRCUITSYNTH compared to various fine-tuned LLM variants. Our approach lays the foundation for future research aimed at enhancing circuit efficiency and specifying output voltage, thus enabling the automated generation of circuit topologies with improved performance and adherence to design requirements.
Paper Structure (32 sections, 7 equations, 2 figures, 2 tables)

This paper contains 32 sections, 7 equations, 2 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Our Approach
  3. Dataset
  4. Model Overview
  5. Circuit Validity Estimation
  6. Generation Enhancement
  7. Circuit Topology Generation
  8. Circuit Topology Refinement
  9. Circuit Validity Estimation
  10. Generation Enhancement
  11. Experiments
  12. Baselines
  13. Zero-Shot Generation
  14. In-Context Learning (ICL)
  15. Parameter-Efficient Fine-Tuning (PEFT)
  16. ...and 17 more sections

Figures (2)

  • Figure 1: An overview of our proposed CircuitSynth. Given a natural language prompt with the component pool, our model can explore the design space effectively and generate circuit topologies by leveraging LLMs.
  • Figure B.1: Example: incident encoding of a netlist.