Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays

TL;DR

This paper analyzes the performance of stateful MAGIC logic in 1-selector-1-RRAM crossbar arrays by developing a Verilog-A 1S1R model that couples a VO2-based IMT selector with a TiN/TiOx/HfOx/Pt RRAM, and by simulating crossbars from $4\times4$ to $512\times512$ including parasitic RC elements. The study demonstrates that 1S1R crossbars significantly reduce power and substantially improve readout margin compared to passive 1R arrays, while preserving or improving switching dynamics for MAGIC NOR operations. Key contributions include a calibrated 1S1R model, detailed crossbar simulations with realistic parasitics, and a quantitative comparison of switching delay, power, and readout margin across array sizes. The results indicate that 1S1R architectures can enable larger, more energy-efficient in-memory computing while mitigating sneak-path effects, making them attractive for scalable MAGIC-based processing-in-memory systems.

Abstract

Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO2-based selector and TiN/TiOx/HfOx/Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from $4\times4$ to $512\times512$. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.

Figures (7)

• Figure 1: (a) Passive RRAM or 1R crossbar array, and (b) active RRAM or 1S1R crossbar array. The selector and RRAM device are illustrated in green and pink respectively.
• Figure 2: MAGIC NOR gates performed over column vectors.
• Figure 3: I-V characteristics of the 1S1R cell. The cell is in HRS for forward sweep and LRS for reverse sweep.
• Figure 4: A 1S1R cell comprising of parasitic resistances and capacitance 9531867.
• Figure 5: Switching delay for NOR(0,1)/NOR(1,0) and NOR(1,1) operation for different array sizes.