Towards Efficient Design Verification -- Constrained Random Verification using PyUVM

TL;DR

This paper evaluates Python-based constrained random verification using PyUVM and PyVSC as an alternative to SystemVerilog-UVM across three IPs (ALU, ADC, ECC). It implements a Cocotb-backed BFM in Python, builds UVM-like environments, and compares feature support, performance, and coverage against SV-UVM with a unified coverage model. The results show that PyUVM can incur longer runtimes due to slower simulator interfacing but offers easier testbench development, introspection, and richer data collection via PyVSC coverage exports. The study highlights both the practical viability and current limitations (e.g., incomplete UVM-RAL, top-level debugging) and points to future opportunities for ML-assisted verification and deeper integration of Python tooling into design verification workflows.

Abstract

Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing Python-based UVM 1.2 implementation and PyVSC facilitating constrained randomization and functional coverage. These libraries play a pivotal role in expediting test development and hold promise for reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs, aiming for a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology.

Figures (7)

• Figure 1: Language complexity with respect to number of specification pages and keywords lang_complex
• Figure 2: ALU
• Figure 3: ADC
• Figure 4: ECC Core
• Figure 5: Proxy-driven PyUVM testbench Fitzpatrick