Effective Design Verification -- Constrained Random with Python and Cocotb

TL;DR

This work assesses the effectiveness of a Python-Cocotb verification setup for three IPs (a $32$-bit ALU, an I2C master/slave, and a $16$-bit ADC) and compares it to SystemVerilog UVM. It analyzes simulator compatibility, feature differences, run-time performance, and coverage quality across multiple simulators, highlighting that cocotb-coverage yields comparable functional coverage to SV while incurring higher run-time due to interfacing overhead. The findings suggest Python-based verification is feasible and practical for CRV and coverage, with caveats around design hierarchy integration, traceability, and support for analog-like real-number modeling. Overall, the work demonstrates that Python-Cocotb can complement SV-UVM for hardware verification, offering easier testbench development and flexible simulator usage with potential for future ML-assisted verification strategies.

Abstract

Being the most widely used language across the world due to its simplicity and with 35 keywords (v3.7), Python attracts both hardware and software engineers. Python-based verification environment leverages open-source libraries such as cocotb and cocotb-coverage that enables interfacing the tesbenches with any available simulator and facilitating constrained randomization, coverage respectively. These libraries significantly ease the development of testbenches and have the potential to reduce the setup cost. The goal of this paper is to assess the effectiveness of a Python-Cocotb verification setup with design IPs and compare its features and performance metrics with the current de-facto hardware verification language i.e., SystemVerilog.

Figures (6)

• Figure 1: Language complexity with respect to number of specification pages and keywords lang_complex
• Figure 2: ASIC verification language adoption VerStudy_22
• Figure 3: Design(s) under test
• Figure 4: BFM class based Python-Cocotb testbench e.g. I2C
• Figure 5: Design Hierarchy