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Parallel Ising Annealer via Gradient-based Hamiltonian Monte Carlo

Hao Wang, Zixuan Liu, Zhixin Xie, Langyu Li, Zibo Miao, Wei Cui, Yu Pan

TL;DR

The paper tackles efficient combinatorial optimization by introducing PHIA, a parallel Ising annealer built on gradient-augmented Hamiltonian Monte Carlo to update all spins simultaneously. By mapping the discrete Ising energy to a continuous Hamiltonian and approximating non-differentiable components with differentiable surrogates, PHIA achieves parallel updates and accelerates sampling, enabling FPGA-based deployment. The authors provide a detailed FPGA implementation on a low-cost board, along with extensive simulations and hardware demonstrations showing sub-linear Time-To-Solution growth and competitive performance against state-of-the-art quantum devices on problems with both integer and fractional coefficients. Overall, PHIA demonstrates a scalable classical accelerator that not only outperforms several existing Ising annealers as problem size grows but also serves as a practical benchmark for evaluating quantum Ising hardware. These results suggest a promising path toward large-scale, hardware-efficient solvers and highlight the potential of gradient-based HMC methods in combinatorial optimization.

Abstract

Ising annealer is a promising quantum-inspired computing architecture for combinatorial optimization problems. In this paper, we introduce an Ising annealer based on the Hamiltonian Monte Carlo, which updates the variables of all dimensions in parallel. The main innovation is the fusion of an approximate gradient-based approach into the Ising annealer which introduces significant acceleration and allows a portable and scalable implementation on the commercial FPGA. Comprehensive simulation and hardware experiments show that the proposed Ising annealer has promising performance and scalability on all types of benchmark problems when compared to other Ising annealers including the state-of-the-art hardware. In particular, we have built a prototype annealer which solves Ising problems of both integer and fraction coefficients with up to 200 spins on a single low-cost FPGA board, whose performance is demonstrated to be better than the state-of-the-art quantum hardware D-Wave 2000Q and similar to the expensive coherent Ising machine. The sub-linear scalability of the annealer signifies its potential in solving challenging combinatorial optimization problems and evaluating the advantage of quantum hardware.

Parallel Ising Annealer via Gradient-based Hamiltonian Monte Carlo

TL;DR

The paper tackles efficient combinatorial optimization by introducing PHIA, a parallel Ising annealer built on gradient-augmented Hamiltonian Monte Carlo to update all spins simultaneously. By mapping the discrete Ising energy to a continuous Hamiltonian and approximating non-differentiable components with differentiable surrogates, PHIA achieves parallel updates and accelerates sampling, enabling FPGA-based deployment. The authors provide a detailed FPGA implementation on a low-cost board, along with extensive simulations and hardware demonstrations showing sub-linear Time-To-Solution growth and competitive performance against state-of-the-art quantum devices on problems with both integer and fractional coefficients. Overall, PHIA demonstrates a scalable classical accelerator that not only outperforms several existing Ising annealers as problem size grows but also serves as a practical benchmark for evaluating quantum Ising hardware. These results suggest a promising path toward large-scale, hardware-efficient solvers and highlight the potential of gradient-based HMC methods in combinatorial optimization.

Abstract

Ising annealer is a promising quantum-inspired computing architecture for combinatorial optimization problems. In this paper, we introduce an Ising annealer based on the Hamiltonian Monte Carlo, which updates the variables of all dimensions in parallel. The main innovation is the fusion of an approximate gradient-based approach into the Ising annealer which introduces significant acceleration and allows a portable and scalable implementation on the commercial FPGA. Comprehensive simulation and hardware experiments show that the proposed Ising annealer has promising performance and scalability on all types of benchmark problems when compared to other Ising annealers including the state-of-the-art hardware. In particular, we have built a prototype annealer which solves Ising problems of both integer and fraction coefficients with up to 200 spins on a single low-cost FPGA board, whose performance is demonstrated to be better than the state-of-the-art quantum hardware D-Wave 2000Q and similar to the expensive coherent Ising machine. The sub-linear scalability of the annealer signifies its potential in solving challenging combinatorial optimization problems and evaluating the advantage of quantum hardware.
Paper Structure (11 sections, 22 equations, 4 figures, 3 tables)

This paper contains 11 sections, 22 equations, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Results
  3. Parallel anealer based on HMC
  4. The FPGA implementation of the parallel annealer
  5. Numerical results
  6. Problem definition for benchmark experiments
  7. The simulation of the parallel annealer
  8. Demonstration of the parallel annealer on FPGA
  9. Discussion and conclusion
  10. Implementation details of the Ising annealer via the discrete HMC sampler
  11. Estimation of the time for a single run on the FPGA

Figures (4)

  • Figure 1: (a) The relation between the energy landscape of the Ising problem and the probability of spin configurations, where a low energy signifies a high sampling probability according to the Boltzmann distribution. (b) HMC method allows a particle to slide on the energy landscape. The final location of the particle is the candidate sampling point and the initial position of the next round of sampling.
  • Figure 2: Schematic of two main blocks in the FPGA implementation. (a) The block that calculates $H(\bm x, \bm v)$. ADDER32 is a 5-stage pipelined logical block composed of 31 ADDER2s. (b) The block that calculates $\dot{\bm v}$. The main latency originates from computing the derivative of the sign function and Eq. (\ref{['quasi gradient']}).
  • Figure 3: The simulation results on different Ising annealers. With the dimension of the problem grows, the PHIA outperforms the other Ising annealers on all types of problems. The TTSs of the GAHMC are much larger than the other annealers, and thus are indicated with a different axis on the right with a different scale.
  • Figure 4: Data of CIM and DW2Q are borrowed from Hamerly2019benchmark. (a) The comparison of TTS on 3 types of problems. $\rm TTS_{PHIA}$ is the TTS of PHIA. (b) Performance of PHIA on various combinatorial optimization problems.