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Resource-aware scheduling of multiple quantum circuits on a hardware device

Debasmita Bhoumik, Ritajit Majumdar, Susmita Sur-Kolay

TL;DR

This work tackles the problem of scheduling multiple quantum circuits on a single m-qubit device while preserving a nearest-neighbor interaction layout and enforcing a buffer to curb crosstalk. It casts intra-device scheduling as an optimization problem, solvable exactly by an ILP that accounts for per-circuit layout noise within a bound ε and a buffer distance b, and shows NP-hardness to motivate a polynomial-time greedy heuristic. The heuristic builds a compatibility graph over circuit-layout pairs and extracts a maximal clique to identify a set of circuits that can run in parallel with low-noise layouts, achieving substantial throughput improvements (about 2x on 27-qubit devices and 3x on 127-qubit devices) with modest fidelity costs (~1–2% for selected benchmarks). The approach demonstrates practical gains for NISQ-era hardware and outlines directions to tune the trade-off between layout diversity and computation fidelity in real-time job queues.

Abstract

Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n < m. In order to prevent cross-talk between two circuits, a buffer distance between their layouts is needed. Furthermore, not all the qubits and all the two-qubit interactions are at the same noise-level. Scheduling multiple circuits on the same hardware may create a possibility that some circuits are executed on a noisier layout than the others. In this paper, we consider an optimization problem which schedules as many circuits as possible for execution in parallel on the hardware, while maintaining a pre-defined layout quality for each. An integer linear programming formulation to ensure maximum fidelity while preserving the nearest neighbor arrangement among interacting qubits is presented. Our assertion is supported by comprehensive investigations involving various well-known quantum circuit benchmarks. As this scheduling problem is shown to be NP Hard, we also propose a greedy heuristic method which provides 2x and 3x better utilization for 27-qubit and 127-qubit hardware devices respectively in terms of qubits and time.

Resource-aware scheduling of multiple quantum circuits on a hardware device

TL;DR

This work tackles the problem of scheduling multiple quantum circuits on a single m-qubit device while preserving a nearest-neighbor interaction layout and enforcing a buffer to curb crosstalk. It casts intra-device scheduling as an optimization problem, solvable exactly by an ILP that accounts for per-circuit layout noise within a bound ε and a buffer distance b, and shows NP-hardness to motivate a polynomial-time greedy heuristic. The heuristic builds a compatibility graph over circuit-layout pairs and extracts a maximal clique to identify a set of circuits that can run in parallel with low-noise layouts, achieving substantial throughput improvements (about 2x on 27-qubit devices and 3x on 127-qubit devices) with modest fidelity costs (~1–2% for selected benchmarks). The approach demonstrates practical gains for NISQ-era hardware and outlines directions to tune the trade-off between layout diversity and computation fidelity in real-time job queues.

Abstract

Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n < m. In order to prevent cross-talk between two circuits, a buffer distance between their layouts is needed. Furthermore, not all the qubits and all the two-qubit interactions are at the same noise-level. Scheduling multiple circuits on the same hardware may create a possibility that some circuits are executed on a noisier layout than the others. In this paper, we consider an optimization problem which schedules as many circuits as possible for execution in parallel on the hardware, while maintaining a pre-defined layout quality for each. An integer linear programming formulation to ensure maximum fidelity while preserving the nearest neighbor arrangement among interacting qubits is presented. Our assertion is supported by comprehensive investigations involving various well-known quantum circuit benchmarks. As this scheduling problem is shown to be NP Hard, we also propose a greedy heuristic method which provides 2x and 3x better utilization for 27-qubit and 127-qubit hardware devices respectively in terms of qubits and time.
Paper Structure (20 sections, 8 theorems, 2 equations, 5 figures, 3 tables, 4 algorithms)

This paper contains 20 sections, 8 theorems, 2 equations, 5 figures, 3 tables, 4 algorithms.

Table of Contents

  1. Introduction
  2. A brief introduction to circuit mapping and layout scoring
  3. Formulation of intra-device scheduling as an optimization problem
  4. Finding the overlap between two layouts
  5. ILP Formulation for our scheduling problem
  6. Obtaining the outcomes of the individual circuits
  7. Noise-aware intra device scheduling is NP-Hard
  8. Polynomial time heuristic algorithm
  9. Generation of the compatibility graph
  10. Greedy algorithm to find a maximal clique in the compatibility graph
  11. Experimental results
  12. Selection of $\epsilon$ for the layouts
  13. Fidelity and hardware utilization in intra-device scheduling
  14. Conclusion
  15. Proof of Theorem \ref{['thm:overlap']}
  16. ...and 5 more sections

Key Result

Lemma 1

The overlap between the two layouts $l_1$ and $l_2$ can be determined by calculating the distance between the boundary qubits of these two layouts only.

Figures (5)

  • Figure 1: An example of a 15-qubit circuit assigned to a 27- qubit hardware. The used qubits are shown in purple while the unused qubits are shown in blue. The hardware still has room to accommodate one or more quantum circuit(s) using the free qubits.
  • Figure 2: The coupling map and bit-wise noise profile of a 27-qubit IBM Quantum hardware
  • Figure 3: Placement of a 15-qubit and a 8-qubit circuit simultaneously on a 27-qubit hardware with buffer distance (a) $b = 0$, and (b) $b = 2$. The former has a significantly higher probability of crosstalk affecting the quality of the computation. The blue qubits are the unused ones.
  • Figure 4: The entire workflow of our heuristic algorithm: (a) schematic diagrams of three circuits that are to be placed in the hardware; (b) two possible layouts for each of the three circuits and their corresponding mapomatic scores; (c) the compatibility graph with edge weights, (d) the connected components of the graph and (e) greedy selection of edges in each of the components.
  • Figure 5: Fidelity (along with the mean and standard deviation) for benchmark circuits (QAOA, Trotterized, Real Amplitude) with and without using our intra-device scheduling executed in (a) Noisy IBMQ simulator with the noise profile and coupling map of 27-qubit IBMQ KOlkata, (b) 127-qubit IBMQ Brisbane hardware.

Theorems & Definitions (8)

  • Lemma 1
  • Lemma 2
  • Lemma 3
  • Lemma 4
  • Lemma 5
  • Theorem 6
  • Lemma 7
  • Lemma 8