Deep Inverse Design for High-Level Synthesis

TL;DR

DID4HLS addresses the challenge of efficiently exploring the HLS design space under multiple objectives by learning conditional design distributions from post-HLS data. It combines PIR-based graph representations with GATv2 predictors and VAEs to model how pragma configurations affect latency and resources, iteratively refining sampling distributions toward the Pareto front. Across six benchmarks, it achieves an average ADRS improvement of 42.8% over strong baselines, demonstrating robust performance and practical synthesis efficiency. The work advances automated HLS DSE by enabling inverse-design-like exploration that respects tool-specific representations and scheduling details, with potential for broader pragma spaces and platform portability.

Abstract

High-level synthesis (HLS) has significantly advanced the automation of digital circuits design, yet the need for expertise and time in pragma tuning remains challenging. Existing solutions for the design space exploration (DSE) adopt either heuristic methods, lacking essential information for further optimization potential, or predictive models, missing sufficient generalization due to the time-consuming nature of HLS and the exponential growth of the design space. To address these challenges, we propose Deep Inverse Design for HLS (DID4HLS), a novel approach that integrates graph neural networks and generative models. DID4HLS iteratively optimizes hardware designs aimed at compute-intensive algorithms by learning conditional distributions of design features from post-HLS data. Compared to four state-of-the-art DSE baselines, our method achieved an average improvement of 42.8% on average distance to reference set (ADRS) compared to the best-performing baselines across six benchmarks, while demonstrating high robustness and efficiency. The code is available at https://github.com/PingChang818/DID4HLS.

Figures (9)

• Figure 1: (a) A toylike code example. (b) PIR of the code.
• Figure 2: An example code with loop labels for HLS.
• Figure 3: Overview of DID$4$HLS. After specifying the design space of an algorithm, the corresponding distributions $\bm{\Theta }$ for sampling pragma configurations are initialized to Uniform. In each iteration, the configurations are combined with the algorithm to generate designs described in C++. Invoking HLS tools generates the PIRs and objectives to augment the dataset for training the predictors and estimators, based on which a surrogate is constructed for updating $\bm{\Theta }$, concluding the current iteration.
• Figure 4: Architecture of the predictors. The PIR CDFGs extracted from HLS results are embedded before input into the deep model based on GATv$2$. The model then outputs graph features for the following MLP to predict the objectives.
• Figure 5: Architecture of the estimators based on VAE. $\mathbf{m}$ and $\mathbf{v}$ output the mean and variance respectively of the Gaussian approximation. The node R signifies the reparameterization trick. $Enc$ represents the encoder. $Dec$ represents the decoder tasked with reconstruction of the graph features $\mathbf{f}$, denoted as $\mathbf{f}^\prime$.