A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX

TL;DR

This work addresses the power and complexity of data detection in mmWave massive MIMO by exploiting beamspace sparsity with SPADE. It presents a $22$FDX FD-SOI ASIC capable of both beamspace and antenna-domain LMMSE equalization, using thresholds $\tau_y$ and $\tau_w$ to prune low-magnitude inner-products. Offline threshold design yields a favorable BER-power trade-off, delivering up to $58.8$ Gbps throughput with body biasing and up to 38% dynamic power savings over antenna-domain processing. Compared with state-of-the-art detectors, the design demonstrates competitive energy efficiency and validates SPADE as a practical, silicon-implementable approach for mmWave MIMO receivers.

Abstract

We present a GlobalFoundries 22FDX FD-SOI application-specific integrated circuit (ASIC) of a beamspace equalizer for millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems. The ASIC implements a recently-proposed power-saving technique called sparsity-adaptive equalization (SPADE). SPADE exploits the inherent sparsity of mmWave channels in the beamspace domain to reduce the dynamic power of matrix-vector products by skipping multiplications for which the magnitude of both operands are below pre-defined thresholds. Simulations with realistic mmWave channels show that SPADE incurs less than 0.7dB SNR degradation at 1% target bit error rate compared to antenna-domain equalization. ASIC measurement results demonstrate an equalization throughput of 46Gbps and show that SPADE offers up to 38% power savings compared to antenna-domain equalization. A comparison with state-of-the-art massive MIMO equalizer designs reveals that our ASIC achieves superior normalized energy efficiency.

Figures (8)

• Figure 1: Beamspace processing in mmWave massive MU-MIMO systems
• Figure 2: Uncoded BER simulation results of LMMSE-A with floating-point operations, fixed-point LMMSE-A and LMMSE-SPADE as implemented in our ASIC, as well as existing baseline algorithms.
• Figure 3: Multiplier activity rate vs. SNR operating point at $1\%$ BER in a $64 \times 16$ system for several threshold pairs for (a) non-LoS and (b) LoS channels. The thresholds for our ASIC measurements were determined offline.
• Figure 4: Top: high-level architecture; bottom: architecture of SPADE-MVM.
• Figure 5: Detailed architecture of one SPADE complex-valued multiplier (CM).