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A Scalable FPGA Architecture for Quantum Computing Simulation

Lee A. Belfore

TL;DR

This work presents a scalable FPGA-based architecture for quantum circuit simulation, targeting large-scale quantum circuits by exploiting FPGA parallelism and a carefully designed data-routing network. It defines a quantum simulation unit (QSU) with modular components (QSR, IM, GIM, GOS, SRPN, 1-QGP, 2-QGP) and validates the design against QuEST, achieving substantial speedups on an Intel Agilex FPGA for up to seven qubits. The approach emphasizes fixed-point arithmetic, a single permutation network, and a universal gate set (Hadamard, CNOT, T) to enable general quantum computation. The demonstrated prototype achieves functional validation, practical FPGA resource usage, and notable performance gains, while outlining clear pathways for scaling, precision improvements, and broader unitary support in future work.

Abstract

A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).

A Scalable FPGA Architecture for Quantum Computing Simulation

TL;DR

This work presents a scalable FPGA-based architecture for quantum circuit simulation, targeting large-scale quantum circuits by exploiting FPGA parallelism and a carefully designed data-routing network. It defines a quantum simulation unit (QSU) with modular components (QSR, IM, GIM, GOS, SRPN, 1-QGP, 2-QGP) and validates the design against QuEST, achieving substantial speedups on an Intel Agilex FPGA for up to seven qubits. The approach emphasizes fixed-point arithmetic, a single permutation network, and a universal gate set (Hadamard, CNOT, T) to enable general quantum computation. The demonstrated prototype achieves functional validation, practical FPGA resource usage, and notable performance gains, while outlining clear pathways for scaling, precision improvements, and broader unitary support in future work.

Abstract

A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
Paper Structure (30 sections, 7 equations, 6 figures, 6 tables, 4 algorithms)

This paper contains 30 sections, 7 equations, 6 figures, 6 tables, 4 algorithms.

Table of Contents

  1. Introduction
  2. Simulating Quantum Circuits
  3. Quantum State
  4. Simple Introduction to Quantum Circuit Operation
  5. Universal Set of Gates
  6. Evaluation of a Quantum Gate on a Classical Computer
  7. General Architectural Decisions
  8. FPGA resources
  9. Algorithm implementation on FPGAs
  10. Permutation network
  11. One and two input gates
  12. Result reporting module
  13. Numerical precision
  14. Verification
  15. Quantum Simulation Unit Architecture
  16. ...and 15 more sections

Figures (6)

  • Figure 1: Top level quantum simulation unit (QSU)
  • Figure 2: Self-routing permutation network for $n=4$
  • Figure 3: One qubit gate pool block diagram
  • Figure 4: Two qubit gate pool block diagram
  • Figure 5: Test circuit schematic
  • ...and 1 more figures