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Invited: Neuromorphic architectures based on augmented silicon photonics platforms

Matěj Hejda, Federico Marchesin, George Papadimitriou, Dimitris Gizopoulos, Benoit Charbonnier, Régis Orobtchouk, Peter Bienstman, Thomas Van Vaerenbergh, Fabio Pavanello

TL;DR

The work addresses the bottlenecks of data movement and energy efficiency in edge AI by proposing neuromorphic accelerators based on augmented CMOS-compatible silicon photonics. It introduces PCM-based non-volatile optical memory and on-chip III-V active devices to realize a photonic in-memory matrix-vector multiply core, exploring multiple MZI mesh architectures for generalized matrix operations. A novel gem5-based simulation framework with RISC-V support (including fault-injection via gem5-MARVEL) enables system-level benchmarking of the photonic accelerator integrated with a host processor. The study provides a concrete pathway toward scalable, high-bandwidth, energy-efficient photonic neuromorphic accelerators and delivers tools for speed, energy, and footprint evaluation within the NEUROPULS project context.

Abstract

In this work, we discuss our vision for neuromorphic accelerators based on integrated photonics within the framework of the Horizon Europe NEUROPULS project. Augmented integrated photonic architectures that leverage phase-change and III-V materials for optical computing will be presented. A CMOS-compatible platform will be discussed that integrates these materials to fabricate photonic neuromorphic architectures, along with a gem5-based simulation platform to model accelerator operation once it is interfaced with a RISC-V processor. This simulation platform enables accurate system-level accelerator modeling and benchmarking in terms of key metrics such as speed, energy consumption, and footprint.

Invited: Neuromorphic architectures based on augmented silicon photonics platforms

TL;DR

The work addresses the bottlenecks of data movement and energy efficiency in edge AI by proposing neuromorphic accelerators based on augmented CMOS-compatible silicon photonics. It introduces PCM-based non-volatile optical memory and on-chip III-V active devices to realize a photonic in-memory matrix-vector multiply core, exploring multiple MZI mesh architectures for generalized matrix operations. A novel gem5-based simulation framework with RISC-V support (including fault-injection via gem5-MARVEL) enables system-level benchmarking of the photonic accelerator integrated with a host processor. The study provides a concrete pathway toward scalable, high-bandwidth, energy-efficient photonic neuromorphic accelerators and delivers tools for speed, energy, and footprint evaluation within the NEUROPULS project context.

Abstract

In this work, we discuss our vision for neuromorphic accelerators based on integrated photonics within the framework of the Horizon Europe NEUROPULS project. Augmented integrated photonic architectures that leverage phase-change and III-V materials for optical computing will be presented. A CMOS-compatible platform will be discussed that integrates these materials to fabricate photonic neuromorphic architectures, along with a gem5-based simulation platform to model accelerator operation once it is interfaced with a RISC-V processor. This simulation platform enables accurate system-level accelerator modeling and benchmarking in terms of key metrics such as speed, energy consumption, and footprint.
Paper Structure (6 sections, 3 figures)

This paper contains 6 sections, 3 figures.

Table of Contents

  1. Introduction
  2. CMOS-compatible SiPh platform
  3. PCM/III-V augmented SOI building blocks
  4. Computing architectures
  5. Simulation platform
  6. Conclusions

Figures (3)

  • Figure 1: CMOS-compatible augmented platform in the NEUROPULS project. Reprinted with permissions from pavanello_neuropuls_2023. IEEE©
  • Figure 2: (a) MZI with the PCM-augmented (in green) non-volatile optical phase-shifters with heaters on top (in yellow) for programmability. (b) An example of an MZI mesh architecture (here implementing $8 \times 8$ matrix) dedicated to accelerating matrix-vector multiplication operations via in-memory optical computing.
  • Figure 3: gem5-based system architecture modeling and simulation infrastructure overview.