Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC

TL;DR

The work tackles real-time spacecraft pose estimation from monocular images on space-ready hardware, employing a co-design workflow that combines mixed-precision quantization with a FINN-based dataflow accelerator to deploy Mobile-URSONet on a Xilinx MPSoC. A layer-wise sensitivity study guides per-layer bit-width allocation, balancing accuracy, latency, and FPGA resource usage. The approach yields a real-time, open-source SPE implementation that achieves about 7.7x speedup and 19.5x energy savings over prior art, with a throughput near 250 FPS and on-chip execution using on-board weights/activations. This contribution advances accessible, energy-efficient autonomous space navigation by providing a reproducible, hardware-compatible SPE solution for in-orbit applications.

Abstract

This article presents a pioneering approach to real-time spacecraft pose estimation, utilizing a mixed-precision quantized neural network implemented on the FPGA components of a commercially available Xilinx MPSoC, renowned for its suitability in space applications. Our co-design methodology includes a novel evaluation technique for assessing the layer-wise neural network sensitivity to quantization, facilitating an optimal balance between accuracy, latency, and FPGA resource utilization. Utilizing the FINN library, we developed a bespoke FPGA dataflow accelerator that integrates on-chip weights and activation functions to minimize latency and energy consumption. Our implementation is 7.7 times faster and 19.5 times more energy-efficient than the best-reported values in the existing spacecraft pose estimation literature. Furthermore, our contribution includes the first real-time, open-source implementation of such algorithms, marking a significant advancement in making efficient spacecraft pose estimation algorithms widely accessible. The source code is available at https://github.com/possoj/FPGA-SpacePose.

Figures (3)

• Figure 1: Methodology that targets FPGA inference
• Figure 2: Modified inverted residual block
• Figure 3: ESA score when only one convolutional layer's weights are binarized, with all other layers and activations at 8 bits