Low-depth Quantum Circuit Decomposition of Multi-controlled Gates

TL;DR

The paper tackles efficient decomposition of multi-controlled gates for quantum circuits on NISQ devices by introducing a borrowed-ancilla, divide-and-conquer framework that reduces depth to $D(n)=O\left(\log^{2.799}(n)\right)$ for ${C^{n}X}$ and extends this approach to ${C^{n}W}$ with $W\in SU(2)$ and approximate ${C^{n}U}$ gates to depth $O\left(\log^{2.799}(n)\,\log(1/\epsilon)\right)$. Key innovations include gate-cancellation through inversion of selected $C^{p}X$ blocks and careful base-case tuning (e.g., $n_b=26$), which together yield lower depth and fewer CNOTs than prior polylog-depth and linear methods. The method achieves its strongest asymptotic results, while experiments on Qiskit and qclib confirm practical gains and reproducibility via open-source code. This work significantly improves the resource requirements for implementing multi-controlled gates, facilitating more scalable quantum algorithms on near-term devices.

Abstract

Multi-controlled gates are fundamental components in the design of quantum algorithms, where efficient decompositions of these operators can enhance algorithm performance. The best asymptotic decomposition of an n-controlled X gate with one borrowed ancilla into single qubit and CNOT gates produces circuits with degree 3 polylogarithmic depth and employs a divide-and-conquer strategy. In this paper, we reduce the number of recursive calls in the divide-and-conquer algorithm and decrease the depth of n-controlled X gate decomposition to a degree of 2.799 polylogarithmic depth. With this optimized decomposition, we also reduce the depth of n-controlled SU(2) gates and approximate n-controlled U(2) gates. Decompositions described in this work achieve the lowest asymptotic depth reported in the literature. We also perform an optimization in the base of the recursive approach. Starting at 52 control qubits, the proposed n-controlled X gate with one borrowed ancilla has the shortest circuit depth in the literature. One can reproduce all the results with the freely available open-source code provided in a public repository.

Figures (8)

• Figure 1: Decomposition of $C^{n} X$ gate with Polylogarithmic-depth from Ref. claudon2024polylogdepth. The circuit comprises the control register $R$, an auxiliary, and a target qubit. The $R$ register is divided into different subregisters: $R_0^* = \{ q_0, \dots, q_{b-1}\}$, $R_0^b = R_0 \backslash R_0^*$ and $b$ subregisters $R_i$, $i \in \{1, \dots, b\}$ with at most $p$ qubits.
• Figure 2: Gate cancelation is achieved by reversing the circuit of the first and third columns of $C^p X$ gates. We analyze the optimization for one line of gates, equivalent to the other lines. After applying the recursion again, the reversal allows the cancelation of two columns of multi-controlled gates in the first and second blocks and the third and fourth blocks. Fig. (a) represents the original recursion in which the gates highlighted in a dashed-dotted line are decomposed in Fig. (b). The last column of the second block and the first column of the third block are also canceled. Rectangles with opaque backgrounds have been added to highlight which gates are undergoing cancelation, Fig. (b). After the cancelations, the resulting circuit for each line of the original $C^p X$ gates has reduced depth and gate counts, as shown in Fig. (c).
• Figure 3: Examples of circuits that can also be optimized. (a) If there are three columns of parallel $C^p X$ gates, each column is decomposed into blocks with a depth of $6\Tilde{D}(k/2^{j+1})$, $5\Tilde{D}(k/2^{j+1})$ and $7\Tilde{D}(k/2^{j+1})$, respectively. (b) If there are two columns of parallel $C^p X$ gates, they are decomposed into two blocks with a depth of $6\Tilde{D}(k/2^{j+1})$. In both cases, the same cancelations are also achieved if the multi-controlled operators acting on the ancilla or the target at the beginning or end of the circuit are absent or if the circuit is reversed.
• Figure 4: Decomposition of an ${n}$-controlled $W$ gate, where $W, A, B, C \in SU(2)$, as described in Ref. barenco_1995.
• Figure 5: Decomposition of an ${n}$-controlled $U \in U(2)$ gate, where $U = V^2$, as described in Ref. barenco_1995.

Theorems & Definitions (3)

• Theorem 1
• Theorem 2
• Theorem 3