Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms

TL;DR

This work proposes leveraging resistive RAM (RRAM) for computing and security by exploiting its Boolean, multi-state, and stochastic properties. It advances digital logic-in-memory (LiM), multi-valued logic (MVL), and hardware security primitives, supported by an EDA framework and hardware prototype that bridge HDL, SPICE-level analysis, and experimental validation. Key contributions include TaOx-based 1T1R gate designs validated experimentally, a multi-state MVL platform enabling a 41-trit adder and finite-state automata, and TRNG/PUF architectures integrated with neural-network weight security on the same crossbar. The integrated framework and prototype demonstrate energy-efficient, crossbar-centric approaches with clear paths toward reconfigurable, next-generation RRAM architectures for computing and security applications.

Abstract

Resistive random-access memory (RRAM) is gaining popularity due to its ability to offer computing within the memory and its non-volatile nature. The unique properties of RRAM, such as binary switching, multi-state switching, and device variations, can be leveraged to design novel techniques and algorithms. This thesis proposes a technique for utilizing RRAM devices in three major directions: i) digital logic implementation, ii) multi-valued computing, and iii) hardware security primitive design. We proposed new algorithms and architectures and conducted \textit{experimental studies} on each implementation. Moreover, we developed the electronic design automation framework and hardware platforms to facilitate these experiments.

Figures (1)

• Figure 1: RRAM for computing and security