NeuroSteiner: A Graph Transformer for Wirelength Estimation
Sahil Manchanda, Dana Kianfar, Markus Peschl, Romain Lepert, Michaël Defferrard
TL;DR
The paper addresses estimating WL for IC placement by solving the NP-hard Rectilinear Steiner Minimum Tree problem. It introduces NeuroSteiner, a Graph Transformer that predicts Steiner points on the $Hanan$ grid and then completes an $RSMT$ by an MST, enabling differentiable WL estimation. The model trains on synthetic nets labeled by GeoSteiner and can be fine-tuned on real nets, achieving about $0.3\%$ WL error and around $0.3$ ms per net on ISPD benchmarks, often beating fast baselines while remaining scalable. It demonstrates a favorable cost–accuracy tradeoff on the WL frontier and highlights the practicality of ML-based WL proxies for placement optimization. The work also shows that training on synthetic data followed by real-net fine-tuning yields robust performance across net degrees.
Abstract
A core objective of physical design is to minimize wirelength (WL) when placing chip components on a canvas. Computing the minimal WL of a placement requires finding rectilinear Steiner minimum trees (RSMTs), an NP-hard problem. We propose NeuroSteiner, a neural model that distills GeoSteiner, an optimal RSMT solver, to navigate the cost--accuracy frontier of WL estimation. NeuroSteiner is trained on synthesized nets labeled by GeoSteiner, alleviating the need to train on real chip designs. Moreover, NeuroSteiner's differentiability allows to place by minimizing WL through gradient descent. On ISPD 2005 and 2019, NeuroSteiner can obtain 0.3% WL error while being 60% faster than GeoSteiner, or 0.2% and 30%.
