Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

A 95.5Gb/s 29.6ns worst-case latency ORBGRAND decoder for 6G xURLLC

Carlo Condo

TL;DR

This work tackles the stringent latency and reliability requirements of 6G xURLLC by advancing a universal, code-agnostic ORBGRAND decoding architecture. Building on LUTGRAND, it introduces out-of-order-output, selective programmability, and aggressive clock gating to achieve a fixed throughput of 95.49 Gb/s with worst-case latency of 29.59 ns and average latency of 13.02 ns in 3 nm FinFET, while reducing area and power by up to ~15–19% and substantially lowering average latency. A key innovation is the use of hardwired 32 non-iLWO error patterns alongside 32 programmable patterns, together with a programmable T_fill to balance BLER and latency, enabling scalable decoding for n ≤ 128 and rate ≥ 0.656. The architecture maintains code-agnostic decoding, supports out-of-order outputs, and demonstrates strong potential for 6G xURLLC deployments where consistent high throughput and low latency are critical. Overall, the approach delivers practical, high-performance, universal decoding suitable for diverse short-code scenarios in next-generation networks.

Abstract

Ultra-Reliable Low-Latency Communications (URLLC) in both 5G and 6G demand high throughput and short latency with low error rates. Guessing Random Additive Noise Decoding (GRAND) and Ordered Reliability Bits GRAND (ORBGRAND) are powerful universal decoding algorithms that work well with short, high-rate codes. As short forward error correcting codes can help limiting latency, and code unification in 6G calls for flexible, possibly code-agnostic decoders, GRAND and ORBGRAND are well suited to tackle 6G URLLC. This work proposes a ultra-high, constant speed ORBGRAND decoder architecture with very low worst-case and average latency. Compared to a baseline architecture, through out-of-order output, aggressive clock gating, and selective programmability, the decoder reduces area, power, and average latency by 15.5%, 19.4%, and 56%, respectively. In 3nm FinFET technology, it achieves a constant throughput of 95.49Gb/s, with 29.59ns worst-case latency and 13.02ns on average.

A 95.5Gb/s 29.6ns worst-case latency ORBGRAND decoder for 6G xURLLC

TL;DR

This work tackles the stringent latency and reliability requirements of 6G xURLLC by advancing a universal, code-agnostic ORBGRAND decoding architecture. Building on LUTGRAND, it introduces out-of-order-output, selective programmability, and aggressive clock gating to achieve a fixed throughput of 95.49 Gb/s with worst-case latency of 29.59 ns and average latency of 13.02 ns in 3 nm FinFET, while reducing area and power by up to ~15–19% and substantially lowering average latency. A key innovation is the use of hardwired 32 non-iLWO error patterns alongside 32 programmable patterns, together with a programmable T_fill to balance BLER and latency, enabling scalable decoding for n ≤ 128 and rate ≥ 0.656. The architecture maintains code-agnostic decoding, supports out-of-order outputs, and demonstrates strong potential for 6G xURLLC deployments where consistent high throughput and low latency are critical. Overall, the approach delivers practical, high-performance, universal decoding suitable for diverse short-code scenarios in next-generation networks.

Abstract

Ultra-Reliable Low-Latency Communications (URLLC) in both 5G and 6G demand high throughput and short latency with low error rates. Guessing Random Additive Noise Decoding (GRAND) and Ordered Reliability Bits GRAND (ORBGRAND) are powerful universal decoding algorithms that work well with short, high-rate codes. As short forward error correcting codes can help limiting latency, and code unification in 6G calls for flexible, possibly code-agnostic decoders, GRAND and ORBGRAND are well suited to tackle 6G URLLC. This work proposes a ultra-high, constant speed ORBGRAND decoder architecture with very low worst-case and average latency. Compared to a baseline architecture, through out-of-order output, aggressive clock gating, and selective programmability, the decoder reduces area, power, and average latency by 15.5%, 19.4%, and 56%, respectively. In 3nm FinFET technology, it achieves a constant throughput of 95.49Gb/s, with 29.59ns worst-case latency and 13.02ns on average.
Paper Structure (7 sections, 3 equations, 4 figures, 1 algorithm)

This paper contains 7 sections, 3 equations, 4 figures, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Proposed decoder architecture
  4. Hardwired patterns
  5. Reduced switching activity
  6. Implementation
  7. Conclusion

Figures (4)

  • Figure 1: ORBGRAND decoder architecture in LUTGRAND.
  • Figure 2: Output selection circuit.
  • Figure 3: Total and additional failed decoding w.r.t. baseline ($T_{fill}=T-1=17$), for BCH(127,113,2) and different $T_{fill}$.
  • Figure 4: Effect of different $T_{fill}$ on the BLER and average output $t$ of BCH(127,113,2).