In-Memory Mirroring: Cloning Without Reading

TL;DR

In-memory mirroring (IMM) enables data cloning inside resistive memory crossbars to resolve data dependencies without engaging energy-intensive read and write-back cycles. By exploiting 1T1R RRAM cells and voltage-configured row/column schemes, IMM supports bit-level and word-level cloning with parallelism, achieving a complexity of $\\mathcal{O}(1)$ for word cloning. SPICE-level validation with the JART VCM v1b model demonstrates substantial energy savings (approximately $10$–$11$ pJ per clone) and a twofold speedup over conventional copying methods, highlighting IMM's potential to dramatically improve energy efficiency and performance in LiM architectures. The study also discusses initialization, compiler-level dependency management, and outlines future experimental validation on fabricated crossbars to confirm practicality."

Abstract

In-memory computing (IMC) has gained significant attention recently as it attempts to reduce the impact of memory bottlenecks. Numerous schemes for digital IMC are presented in the literature, focusing on logic operations. Often, an application's description has data dependencies that must be resolved. Contemporary IMC architectures perform read followed by write operations for this purpose, which results in performance and energy penalties. To solve this fundamental problem, this paper presents in-memory mirroring (IMM). IMM eliminates the need for read and write-back steps, thus avoiding energy and performance penalties. Instead, we perform data movement within memory, involving row-wise and column-wise data transfers. Additionally, the IMM scheme enables parallel cloning of entire row (word) with a complexity of $\mathcal{O}(1)$. Moreover, our analysis of the energy consumption of the proposed technique using resistive random-access memory crossbar and experimentally validated JART VCM v1b model. The IMM increases energy efficiency and shows 2$\times$ performance improvement compared to conventional data movement methods.

Figures (7)

• Figure 1: (a) schematic for implementing the OR operation within the crossbar architecture, utilizing three memristors. Two memristors are designated as inputs, while the third is output storage. (b) The crossbar architecture demonstrates the parallel execution of the same operation. (c) The challenge of data dependency and proposes a solution by transferring data between devices within rows and/or columns.
• Figure 2: (a) RRAM schematic for cloning. (b) the approximate equivalent circuit.
• Figure 3: Different configurations of crossbar architectures. In (a), the vertical crossbar layout is presented, wherein the gates of transistors are connected vertically. (b) Bit-cloning in the vertical crossbar. (c) Horizontal crossbar, characterized by horizontally connected transistor gates. (d) Bit-cloning in horizontal crossbar
• Figure 4: (a) 3x3 crossbar array structure sketch. The gray arrow exemplifies the voltage source. The colored circle at the junction represents different memristors' states. (b) Method of bit cloning in the same row, where the data is marked as "A," which will be moved according to the representation of the green arrow. (c) Row-wise bit operations and the dotted blocks show the unselected rows and columns. (d) Column-wise bit operation where only one-bit value will be moved is marked in the green arrow. (e) Selected voltage source and devices to perform the column-wise bit cloning. (f) Representation of full column movement where the first complete row word will move to the third row in parallel. (g) Selection of the required cell to perform word cloning. (h) final state after performing all operations from (a) to (g) in a sequence
• Figure 5: (a) 1T1R cell schematic, (b) material stacks of memristor, (c) I-V characteristics for 100 cycles